• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 49 subscribers
  • Views 490 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

linearity problem with the ADC12D1800RF

dan ohev zion
Prodigy 105 points

Other Parts Discussed in Thread: ADC12D1800RF, ADC12D800RF, ADS5400, ADC12D500RF, ADC12D1800

Hi,

I am using the EVB for the ADC12D1800RF, and noticed a problem with the HD3 performance:

sampling rate is 1800MSPS, with test signal at 124MHz.

when signal level is -1dBFS, the HD3 is about -70dBC (after I perform calibration).

when signal level is lowered to -25dBFS, the HD3 becomes -50dBFS, meaning it still has about same power, despite of the signal power reduction.

same thing happened when I changed signal frequency to 248MHz etc.

note that I'm using the EVB along with the balun EVB (that has 1:2 transformer+100ohm resistor on it), with external DC-Blocks.

can you explain this odd HD3 behaviour?

  • 0
    TI__Genius 13335 points

    Hello ddd,

     This behavior is expected with a folding and interleaving ADC architecture. The harmonics measured by the ADC are a combination of the input track and hold stage (which are linear) and from the inherent nature of folding and interleaving (non-linear).  You can see from the below plot that the harmonics are mostly dominated by the latter non-linear harmonics. In fact changing the input level hardly has an impact on the level of the harmonics.

     

     

    You can read more about where the harmonics come from and methods of mitigation in the following application report: 

    Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigation (http://www.ti.com/lit/an/slaa617/slaa617.pdf)

     Please read the report and let us know if this answered your question.

     Thanks!

  • 0 in reply to Luke LaPointe
    Prodigy 80 points

    Hi,

    App note SLAA617 seems to be the first place that there has been any mention of these ADCs using interleaving in the dual-channel mode, i.e. the dual device actually uses four ADC sections. This is rather disappointing for those of us looking for clean spectra from 1Gs/s - plus converters.


    Please can we have some better ADCs soon?

    Regards

  • 0 in reply to Simon Rundle
    TI__Genius 13335 points

    Hello Simon,

    We have non-interleaved folding-interpolating ADCs like the ADC12D800RF and ADC12D500RF. We also have a 1GSPS pipeline ADC, ADS5400.

    What specific requirements are you looking for? Architecture? Sampling rate? Resolution? Power consumption? This would be helpful to navigate our current portfolio or feed this information to our next generation product definition team.

    Thanks!

  • 0 in reply to Luke LaPointe
    Prodigy 80 points

    Hi Luke,

    Specifically, at the moment, 3.3Gs/s, like the ADC12d1800 but with better SFDR.

    Ideally but realistically, 16 bits, 10Gs/s, SFDR 90dB, power  <1W, NO calibration tweaks, analogue bandwidth flat to Nyquist,etc. Oh, cost < $100 (1 off).  If you could arrange for it to bolt directly on top of a 1Megathing FPGA that would be nice.

    Well, you did ask.....


    Regards,