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DAC8822 update rate

Guru 20090 points

Other Parts Discussed in Thread: DAC8822

Hello,
 
 
Could you please kindly let me know about update rate of DAC8822 ?
Please see the attached file.
 
<Question 1>
This timing diagram is for one time conversion.
Is my undersanding of update rate in attachment correct ?
 
<Question 2>
Please let me know update rate when DAC8822 convert continuously.  
Is it same with one time converstion ?
We make any stable time for DAC8822?
 
If my question is unclearly, please let me know.
 
Best Regards,
Ryuji Asaka
  • Hello Ryuji,

    1. This timing diagram is for one time conversion. Is my understanding of update rate in attachment correct?
      1. This is correct assuming you are combining the LDAC and !WR pins together or if LDAC is permanently tied high. Otherwise, the LDAC minimum pulse width must also be included in the calculation. 
      2. Additionally, this is making the assumption that you require that the DAC output is settled to 0.0015% FSR, or 1 LSB, and that the output is transitioning from zero-scale to full-scale. For cases that the output is transitioning over a smaller code range the output will settle faster. The value you have calculated is a good worst case figure for the longest it will take for you to write a value to the DAC and for the output to fully settle. 
    2. Please let me know update rate when DAC8822 convert continuously. Is it same with one time conversion? We make any stable time for DAC8822?
      1. You should be able to write to the DAC as quickly as the digital interface allows. Based on the timing diagrams this is 50MSPS. Of course, in this case the output does not ever fully settle. In your case where you are waiting for the full-scale settling time before writing another update, your calculation in your attachment holds true.

    Let me know if you have anymore questions.

  • Hello Kevin san,
     
    Thank you very much for your reply.
    Are below my understandings about your reply to Qustion 2 correct ?
     
    If we use LDAC as Load the DAC register ,  we must add the LDAC minimum pulse width to 50MSPS.
    Thus, update rate of the logic ( don't consider the settling time) will be 33.3MSPS (30ns).
     
    summary
     -/WR and LDAC pins tied together or LDAC is permanently tied hith :  50MSPS
     -Otherwise : 33.3MSPS
     
    Best Regards,
    Ryuji Asaka
  • Asaka-san,

    Your understanding is correct.

    Please let me know if there is anything else I can help you with.

  • Hello,
     
    Thank you for your prompt reply.
    I understood.
     
    Best Regards,
    Ryuji Asaka