ADS1148 DRDY and SPI ADC data issue

Hi Vishal,

Welcome to the forum!  If the ADS1148 is powered on with AVDD and DVDD, which it appears to be by your description, and if the internal oscillator is running (which also appears to be active by your description), then you should see DRDY pulse.  I'm not sure how you are trying to probe the DRDY line as it does not appear that you have test points according to the schematic. I do know it is difficult to get a good probe contact with QFN devices by probing directly on the device.

You are likely to get all FFs if you are not using the internal reference.  The default is the REFP0, and I see you have it connected to ground.  You not only have to turn on the internal reference, but you must also select it as the reference to use for conversion.

Can you send me the register settings you are using?  Can you also send me some scope shots of your communication?

Thanks,

Bob B

Hi Bob,

Thanks for quick response. Today we erased whole code in microcontroller and power on board. Now at least we can see 5 pulses per second on DRDY line as mentioned in datasheet. So power on behaviour of ADC looks correct.

Now the problem is we are not sending any stop conversion command which should stop continuous conversion. Now we assume it seems to be a firmware issue, but can you please suggest if ADC can interpret some wrong command and hang and stops conversion at all? Is this possible? Or what could cause ADC to stop pulses on DRDY line?

Right now I don't have code with me, but I will give you register settings tomorrow morning. Also we are turning ON internal reference as well as we are using it as a reference.

Thanks,

Vishal

Hi Vishal,

START pin low will stop conversions, as does the SPI SLEEP command.  As a point of clarity, the SDATAC command does not stop conversions.  It stops placing the conversion results automatically to the output register.  This means DRDY should still pulse even if a SDATAC command has been issued.  RDATAC (default mode) automatically posts the result to the output register so data can be read directly by sending SCLKs without an associated command.  In SDATAC mode, this behavior stops and the RDATA command is required to retrieve the data.

The SPI SLEEP command will discontinue if it is accidently issued as soon as CS goes back high.  So I'm really not sure what might be happening at this point with the information I available.

Best regards,

Bob B

Hi Bob,

 I have prepared sequence with least no of commands to try. Its a combination of sequence + checklist that we need for ADC reading... Can you please check steps?

· Ensure SPI polarity bits in microcontroller side:
CPOL = 0 i.e. clock is normally low

CPHA =1 i.e. data is changed on rising edge of clock and is stable on falling edge of clock.

· Ensure Start pin is high and reset is also high (this is not actually critical)

· Ensure we wait for at least 16ms after start pin goes high (power up)

· Check Pin no 31 of ADC on oscilloscope, it should give 5 pulses per second as our default sampling rate is 5SPS.

· Issue write register command : 0x42 (Select register address of Mux1)

· Send next data byte : 0x00 (to instruct that only Mux1 register has to be written)

· Send MUX1 register value = 0x30 ( Select internal reference voltage, normal operation)

· Issue write register command : 0x4A (Select register address IDAC0)

· Send next data byte : 0x01 (to instruct that 2 registers have to be written IDAC0, IDAC1)

· Send IDAC0 register value = 0x0F (in case DRDY/DOUT multiplexed, 1.5mA current source)  (Initially prefer this mode)

                                               0x07 (in case DRDY disabled, only DOUT, 1.5mA current source)
· Send IDAC1 register value = 0x01(to connect current sources to AIN0/1)

· Ensure CLK line is low for at least 244ns (1/fclk) before DRDY goes low.

· Wait for DRDY goes low.

· Also check DOUT line. If it is high, it should go low. If it is low, then it will go high and again go low. Our sampling rate is 5sps, so we should see this behaviour 5 times per second.

· Wait for DRDY goes low.

· Issue NOP command: 0xFF (Read MSB) (we will try to use default continuous read mode of device, even if we do not read it properly because of some SPI setting issue, we should see some transitions on scope)

· Issue NOP command: 0xFF (Read LSB)

Regards,

Vishal

Hi Vishal,

The programming flow as you have shown it should work fine.

Best regards,

Bob B

Hi Bob,

Today we made some progress on ADC writing part. Now we can write to ADC, turn on internal reference, change sampling rate. We verified that pin no.31 (DRDY line) sampling rate changes when we send SPS change command. But as soon as we try to read data form ADC, we can see no action on DRDY line. It seems to remain high. It doesn’t toggle at all. One thing that I can think that is it possible that we are trying to read data at very fast rate than DRDY toggling rate and that puts line inactive? But ideally we should read wrong data, but it should not cause DRDY line to stop responding completely. Can you please suggest on this?

Second problem: When we configure DOUT line as DOUT/DRDY multiplexed line, we do not see any transition on DOUT line. Pin no.31 (only DRDY) line toggles at specified sample rate, but DOUT- DRDY line never toggles. Also line does not go to 3.3V level. It seems to be at 2.5V. Can you suggest on this?

Third Problem: We have 2 ADCS on board. Both are on same SPI port. Now DOUT/DRDY line of both ICs are tied together and connected to controller (there is one more device on same SPI with different chip select). So if we try to configure DOUT line for DRDY function for both ICs, both ICs simultaneously try to control single line. I assume chip select function should be applicable only when line is used for DOUT purpose. When line has DRDY function, it will generate pulse when chip select is high. So is there any limitation that if we need to use DOUT line multiplexed for both DOUT/DRDY function, we should connect only single device on SPI port. Is it limitation? I hope I am able to explain a problem. If you need some more explanation, please let me know.

Thanks for your support.

With regards,

  Vishal

Hi Vishal,

The normal behavior for DRDY is to go high after the first SCLK is received.  However, it should go low again after the next conversion cycle completes.  One thing to consider when connecting multiple ADS1148 devices to the same SPI bus is that irregardless of the CS, DRDY will go high once it sees the SCLK.  This means that all devices will signal DRDY high no matter if CS is selected or not.

If DOUT/DRDY does not follow DRDY when bit 3 of the IDAC0 register is set, then either the configuration is incorrect for IDAC0 or there is a connection issue.  If DOUT/DRDY only goes to 2.5V, I would suspect either a wiring connection issue or more than one device with CS low.  Verify and make sure that only one CS is low or there will be output driver contention.

The datasheet specifies on page 36 in the DOUT/DRDY section that when CS is high the output is in a high impedance state no matter which output mode is selected. If you are seeing the issue of driver contention, then more than one output is active at a time, and this is controlled by the CS signals.

Best regards,

Bob B

Hi Bob,

Thanks for reply...

I am bit confused here. I have two ADCs connected on same SPI. I enable DRDY function on DOUT pin for both of ADCs. Now I do not enable any of chip selects. DOUT of both ADCs is same and goes to MISO pin of processor. So when data conversion for 1st ADC is complete, it will try to pulse DRDY line, but if another ADC is yet to complete conversion, it will try to keep line low. Is it not a problem? Or we can not see DRDY pulses on DOUT line unless CS is active. In this case, only one ADC can drive DOUT line at a time.

Or do we need to use Sync command so that both ADCs complete conversion at same time. This should work only if SPS is same for both of them. Otherwise it can fail. Please suggest.

Basically I want to know DOUT/DRDY function in case chip select is inactive and active.

With regards,

  Vishal

Hi Vishal,

DOUT/DRDY is tri-state when CS is high.  The DRDY pin is an active output pin at all times.  You cannot tie two active output pins together or they will fight against one another (contention).

As you have mentioned, you can SYNC the devices together and use just one DRDY pin or the DOUT/DRDY.  To keep the devices in SYNC they will need to use the same clock source.  This can be done with an external oscillator connected to each of the devices CLK input pin.  The easiest way to start conversion is to use the START pin for synchronization.

Best regards,

Bob B

Hi Bob,

Thank you very much for all your support. Today we made good progress and now we are able to read correct data from ADC. But we are facing one problem. When we try to detect open RTD channel, we turn on burn out current sources, so we expect to read 0x7FFF on open RTD channel, but we always read 0xFFFE. We tried turning off burn out current source, but still we read same data. Can you please suggest what data should we read in case of open RTD and short RTD? Can you please suggest what can cause this issue?

With regards,

  Vishal

Hi Vishal,

0xFFFE is basically a shorted input condition.  What exactly do you have connected to your input? Which inputs are you using?  How have you been exciting the RTD?  And what are your registers settings that you are using?

A shorted input condition may occur if the mux input is accidently connected to the same channel for both AINP and AINN.

Best regards,

Bob B

Hello Bob,

We have connected resistors across AIN0-1, AIN2-3. We can read proper value on these channels. AIN4-5 and AIN6-7 are open, there is no RTD connected across these channels. I don't have register setting with me right now, but with this condition, what should we read? 0x7FFF???

With regards,

 Vishal

Hi Vishal,

With a truly open condition you should read positive full-scale (0x7FFF) with the burnout current sources enabled.  In this condition AINP is pulled toward AVDD and AINN is pulled to ground.  This should produce a full-scale result.

Best regards,
Bob B

Hi Bob,

We have 3 wire RTD connection. So we connect 1^st terminal to AIN0 and 2^nd terminal to AIN1. Normally we connect this 2^nd terminal to Ground also. In this configuration, we can read proper data. Now to generate open condition, we opened RTD connection across AIN0 and AIN1. We also removed AIN1 and GND connection. In this case we read FFFE data. So today we connected GND to AIN1 and kept open between AIN0 and AIN1. So basically we simulated RTD element open condition. So in this configuration, we could read 7FFEi.e. close to full scale as expected. We did not turn on burn out current source. With burn out current source enabled, we should read 7FFF.

Same case in case of RTD short. If we just create short between AIN0 and AIN1, and do not connect AIN1 to GND, we read FFFD, but we connect AIN1 to GND, we read 0000.

Do you suspect anything wrong in this observation? Otherwise we can read correct data from all channels of both ADC.

Thank you very much for all your support. You have really helped us to resolve issues.

With regards,

  Vishal

Hi Vishal,

One thing to keep in mind when using the ADS1148 is that there is a common mode input range restriction.  You cannot use a single supply voltage for the analog supply and then connect any of the inputs to ground as a part of the measurment.  See the information in this section:

http://e2e.ti.com/support/data_converters/precision_data_converters/w/design_notes/1370.input-voltage-range-requirements-for-the-ads1248-and-ads1148-families.aspx

So the statement about reading proper data is incorrect when one of the inputs is tied to ground.  You must bias the sensor (whether it be a resistor, thermocouple or RTD) into the correct common mode input range.  If you are using the IDACs for sensor excitation, then you must also add a resistor between the sensor and ground so that the measurement is within the correct common mode range.  Be careful with the value as there is also a IDAC voltage compliance requirement (about 1V below the analog supply) where the total voltage drop created by the sensor/bias resistor combination meets the compliance requirement. 

As a side note, the bias resistor is often used for establishing an external reference so that the conversion result becomes a ratiometric measurement.

Your original schematic that you posted shows no input filtering ( you most likely will want to add at least anti-aliasing).  If this is still the case, and you connect a 100 ohm resistor across the AIN0 and AIN1 inputs you will need some place for the current to travel.  So also connected to the AIN1 input is a 2k resistor where the other end connects to analog ground.  This completes a current path for the current source.  If the IDAC is turned on to 1mA output, and is sent out AIN0, then you will see 100mV dropped across the AIN0 and AIN1 and 2V dropped across the 2k bias resistor.  With a 5V analog supply this will set the common mode close to mid-supply and also the total voltage drop will be within the IDAC compliance voltage.

If you turn off the IDAC current and turn on the burnout sources, you will see a voltage drop across the 100 ohm resistor somewhat relative to the value of current chosen, but the measurement is not totally valid as it is now referred to ground (now outside the common mode range).  You should see no voltage drop across the 2k bias resistor as the current source will pull the current to ground through the AINN input that is sourced from the AINP input.  If you short the resistor, you should see about 0V input (plus noise and the non-linearity of the input still referred to ground) and for an open you should see full-scale as there is no current path.  This happens because of the open that pulls one source toward AVDD and the other that is pulling the source toward AGND.  This actually is overdriving the input beyond the reference value and that is why it becomes full-scale.  If you do not see full-scale in this condition, then you have some sort of leakage path which might be created by your input protection diodes.

Best regards,

Bob B

Hi Bob,

Thank you very much for this important information... Actually today we tried increasing PGA gain of ADC. Till now we were using PGA gain of 1. But readings are not successful with any other PGA gain other than 1. For e.g. with PGA gain of 1, for 0.2425 volts, we get reading data output as 3881. Now with PGA of 2, we expect data output as 7762. But we got data as 5186. So its not double but around 30% high than PGA gain of 1. All channels have same behaviour. So we triedby increasing PGA gain. There is a relative increase in output data, but not exactly 2 times,4 times or 8 times. So do you suspect this behaviour because we don't have bias resistor? or what can be the possible problem?

With regards,

  Vishal

Hi Vishal,

This is exactly the type of behavior you will see when saturating the PGA.  The ADS1148 has a PGA that is similar to an instrumentation amplifier.  With one input grounded, the output of the amplifier cannot get to the desired voltage level.  As gain is applied the problem gets worse.

You need to make sure that your input is within the required common mode input range for the ADS1148.  As you increase gain, the usable voltage range narrows so it is best to make sure that the common mode is near mid-supply of AVDD.  The biasing resistor will set the sensor into the correct common mode range.

Best regards, 

Bob B