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DDC114 noise issue

thilak raj1
Prodigy 170 points
Other Parts Discussed in Thread: DDC114, TMS320F28335

hello

we are using DDC114 for one of our project,data sheet  recommends the CONV toggle should be within +- 10ns of the rising edge of the CLOCK,since CLOCK is 4MHz,we are unable to achieve it using TMS320F28335,The CLOCK is connected to GPIO0/EPWM1a and CONV is connected  to GPIO1/EPWM1b.The DDC114 is connected to Hamatsu S1337 Photo diode,we have pulled up the all the RANGE pin to VCC.

regards,

Thilak

  • 0
    TI__Guru 65250 points

    Hello Thilak,

    Thanks for posting, sorry for the delay. Just to make sure I understand your situation:

    You're using the DDC114 in range 7 (all 3 range bits held high) and you are seeing higher noise than you expect. What noise values are you getting? CONV vs CLK timiing is essential for low noise operation. Having not used the TMS320F28335 I am not familiar with it, can you use it to divide down the CLK signal internally to generate CONV so that the two signals are synced? You might need to look into other clock options such as a discrete CLK generator chip which offers dividers. For now you can experiment with a synced bench CLK generator or something similar. Hope this helps, let me know and I can provide more information.

    Regards,

    -Adam Sidelsky