Unexpected behavior when ADS1282 Sync coincide with 4MHz clock rising edge

I have experienced a very strange behavior on one of the ADS1282 device.  When the rising edge of the sync signal coincide with the 4MHz clock rising edge.  The ADS1282 will begin generate data ready (DRDY) around 3 - 5ms (varies each time) after the rising edge of the sync signal, instead of the normal 63 sample time after the sync signal.  

I noticed on the data sheet there should be a 10ns delay between the Sync signal and the clock rising edge.  But do you expect this kind of behavior if we violate the 10ns.  

Thanks