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ADS8363: CONVST relative to CLOCK

Ian Lewis
Prodigy 60 points
Other Parts Discussed in Thread: ADS8363, ADS8361

The ADS8363 has a specified setup time, t1, for CONVST to CLOCK. As far as I can see, meeting this spec is mandatory. If this is so, then it is not possible to capture the source signals on an arbitrary event since such an event would have no relation to CLOCK.

Is this correct? That is, can ADS8363 only be used where one has control of when to transition to hold mode?

Ian Lewis
www.mstarlabs.com

  • 0
    TI__Guru**** 181401 points

    Hi Ian!

    The sampling instance for the ADS8363 is not actually dependent on t1 from the standpoint of the CLOCK input.  The t1 setup time is related to the point at which the conversion actually begins - the entry is there in order to help define the timing parameters needed to achieve full speed operation of the ADS8361 device.  If you happen to miss the t1 setup time, the conversion will start with the next rising CLOCK edge, but the sample and hold switch opens regardless of the CLOCK state, indicated by BUSY going high.

  • 0 in reply to Tom Hendrick
    Prodigy 60 points

    Thank you, Tom.

    So, just to be clear, there are no internal metastability issues in ADS8363 with missing t1. Transition to hold occurs on the rising edge of CONVST regardless of the state of CLOCK. Acquisition throughput goes down by one CLOCK cycle, but otherwise operation proceeds normally if you violate t1.

    Maybe I missed it, but I saw nothing in the data sheet to indicate that t1 is advisory for obtaining maximum throughput. Assuming I have understood, then TI should add that information to the specification.

    Ian Lewis
    www.mstarlabs.com

  • 0 in reply to Ian Lewis
    TI__Guru**** 181401 points

    Hi Ian,

    Yes, that is correct, the sample period ends with the application of CONVST regardless of the clock.  CONVST is an asynchronous input.  I'll see what we can do to further clarify this either in the data sheet or through an application note.    The text under the CONVST section on page 17 describes the conversion starting one CLOCK rising edge late if the RD+CONVST signals are tied together and synchronous to the rising clock edge (i.e. when violating the t1 setup time).