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ads42lb49 syncinp input in QDR mode

marcin.slusarski
Prodigy 20 points

Other Parts Discussed in Thread: ADS42LB49

Hello,

I am currently working on interface for ads42lb49 ADC (Xilinx fpga), and I am having problem with understanding SYNCIN pin.

Configuration of adc:

- QDR mode

- 200 MHz clk into ADC (200 MSPS), no internal division

I read in other data sheets, that SYNCIN pin is used to synchronously sample analog data, in case of using multiple adcs.

Q0: If I do not use internal division of clock (inside ADC), is it required to drive this signal, or just connect SYNCINP to GND and SYNCINM to AVDD. If data is always captured at rising edge of CLKINP, do I need to synchronize it? Or in which cases I should synchronize it?

Q1: If I would like to use more than one adc, I assume that,  I should drive all of SYNCINP, SYNCINM pins with one signal from FPGA? Or is it unnecessary, because of no ADC internal CLKIN division, and if I imply that CLKIN is synchronous at input pin of every ADC?

Q2: Is it recommended to connect SYNCIN pins? If yes, in which cases?

Q3: Do I need to assert SYNCIN signal after power up?

Q4: If SYNCIN is used, does sync delay register (SYNCIN DELAY, addr 0x7) is meant to be used when I need to compensate path delay?

  • 0
    TI__Genius 17470 points

    Hi Marcin,

    Sorry for the long delay. We've had quite a few questions about the SYNC input, so we'll need to add a description to the datasheet.

    Let me clarify with the design team before I lead you astray.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    TI__Genius 17470 points

    Hi Marcin,

    The SYNC input is meant to synchronize the clock dividers among multiple chips, such that the phase of the divided down clocks match between ADCs. If the clock divider is not being used then the SYNC input is not required to achieve multi-device synchronization. If you are not using the clock dividers then SYNCP can be tied low with a pull-down resistor, and SYNCN can be tied high with a pull-up resistor. Additionally, the SYNCIN EN bit in register 0x30 can be set to 0 to disable the SYNC input.

    Here are the rules for device synchronization:

    1. Sampling clocks to all ADCs must be phase aligned
    2. If the internal clock divider is used, the clock dividers in all devices must be reset at the same point in time to guarantee phase alignment at their output.

    Number two means that an edge (pulse or square wave) needs to appear on the SYNC input at the same point in time at all ADCs and meet setup and hold times relative to the device clock. The SYNCIN DELAY can be used to adjust the setup and hold times of the SYNC signal relative to the device clock to guarantee capture on the correct device clock edge.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 20 points

    Hi Matt,

    Thank you for your answer. It is very helpful.

    Kind regards,

    Marcin Ślusarski