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ADS62P49 Parallel Configuration (only)

Peter Kortekaas
Prodigy 95 points
Other Parts Discussed in Thread: ADS62P49

I'm having trouble with parallel configuration on the ADS62P49. I can do serial configuration, but in some application the number of control signals is limited and I need to use parallel configuration. Serial configuration works fine, but parallel configuration doesn't.

I have tied RESET high, SCLK low, and SEN to (5/8)AVDD. With CTRL1-3 pins I select MUX mode (111). Now all channel A works fine, channel B give strange results. Doing some experiments leans that the device seems to work corrent when RESET is tied low. I do not understand why, since the datasheet tells me RESET should be tied high (page 14).

Another strange behaviour related to the reset is the output format. When RESET is kept high, the output format is offset binary CMOS, but is should be 2's complements according to table 5 in the datasheet. But when RESET is tied low, the output format is 2's complement.

So I have two reasons to assume the reset should NOT be kept high for parallel configuration only, but I like to have a confirmation on this. I need to be sure if there is a risk not resetting the device.

Thanks,

Peter

 

 

 

 

  • 0
    TI__Expert 3865 points

    Peter,

    we are checking into this now and would like to get clarification on a few things from you:

    1. In mux mode (with RESET,CTRL1,2,3 all high), data on chB output datalines(DB0 to DB13) is strange , or chB data which comes on chA datalines is strange? Both channel A & B data will get multiplexed and output on channel A (DA13 to DA0).
    2. What speed are you operating the mux mode at? You should not operate at a speed >65Msps else it may result in poor output timings(setup/hold violations)
    3. How are you forcing SEN to 5/8AVDD, as SEN has a ~150k pull-up resistor to AVDD which makes offset binary/CMOS output as default when RESET =1 ?

    Best regards,

    Thomas Neu

  • 0 in reply to Thomas Neu
    Prodigy 95 points

    Hi Thomas,

    I'm so glad you’re looking into this issue. See my answers and some additional information below.

    1.       It is chB which comes on datalines DA13 to DA0 which is not correct. I am pretty sure it is not a timing issue in my FPGA, because I also did a test with reset low. In this test chA as well as chB is correct. With reset low the internal register 0x40 defaults to 0000 which means pins CTRL1-3 determine the mode. So I am also sure the CTRL1-3 pins are setup correctly.

    2.       We sample at 62.5MHz.

    3.       SEN is driven to 1.8V by an active component.

    Regarding the RESET, I have a question, because the datasheet is not clear to me. On page 9 is says the RESET input supports 1.8V CMOS logic level, but page 14 tells me the RESET needs to be tied to AVDD. When RESET is high in my case I actively drive it to 1.8V. This couldn’t be the issue, right?

    Another issue I was thinking of; it seems that the default setting for LOW SPEED is disabled. Is LOW SPEED automatically enabled when multiplexed mode is selected in parallel configuration?

    Thanks, Peter

  • 0 in reply to Peter Kortekaas
    TI__Expert 3865 points

    Peter,

    any chance you can send us a snapshot of the schematic also?

    Thomas

  • 0 in reply to Thomas Neu
    TI__Expert 3865 points

    Peter,

    yes my email address is tneu@ti.com

     

    Thomas Neu

  • 0 in reply to Thomas Neu
    TI__Expert 3865 points

    Peter,

    I studied your schematic and came across something. Yuo have SEN signal come from the 1.8V translator. SEN determines if you are running the output interface in CMOS or LVDS. Assuming 3.3V analog supply, you may not achieve the voltage level required to place the ADC output in the right mode. Are you trying to achieve CMOS offset binary?

    One thought we had is with reset pulled low, you are placing the ADC in serial config mode and the default is CMOS. You may override the control config with the external pins to place the ADC in mux mode which may explain what you are seeing.

    Can you try a 3.3V signal on the SEN pin (as well as SCLK pin probably)?

    Thomas Neu

  • 0 in reply to Thomas Neu
    Prodigy 95 points

    Hi Thomas,

    I needed to scratch my board, but I was able to do a test with SEN high to 3.3V. This indeed works fine with MUX mode enabled. So indeed the 1.8V is the problem. Likely 1.8V level is slightly out of 5/8*AVDD range.

    What about the LOW SPEED mode? Is it automatically enabled in MUX mode (when enabled though the parallel interface)?

    Thanks for your help so far!

    Peter