DAC7811 Readback

Hi John,

The timing table can be found on page 3 of the DAC7811 datasheet.

Daisy-chain mode does not need to be enabled or disabled in order to read-back.

Just use the command: 0x2XXX (X = Don’t care.)

SDO will output the value of the DAC register in the following clock cycle.

If you are still experiencing issues, it would be helpful if you could share a schematic of the circuit and some scope captures of the digital pins.

Regards,

Hello,

It appears everything is working if I put the DAC7811 in the standalone mode immediately after power up. If I don't send the command to disable daisy chamin mode, the DAC will only accept the first command. After the first command, it will ignore subsequent commands until I cycle power to the DAC.

I am using the DAC7811 EVM evaluation board with an IAR STM32F407 development board. The SPI signals are connected by jumper wires and are noisy.

This is the scope capture, the top trace is SDIN, middle trace is the SYNC, and bottom trace is SCLK.  I sent 0x1400 to set the output to +5V on the first command. The second command was 0x1c00 to set output to -5V. In the default daisy chain mode, the output voltage stays at +5V. If I first send the command ox9000 to disable the daisy chain mode, the output switches from +5V to -5V as expected.

Thanks.

I tried replicating the behavior that you observed.

The plot above is with right after power-on with Daisy Chain enabled (default).

I alternated between the commands 0x1800 (Write, 0V) and 0x1000 (Write, -10V).

The part was functional after any write command with Daisy Chain enabled or disabled.

Do you think I could take a look at the schematic that you are using in order to make a better assessment of the issue?

Please see the following link for the schematic of the IAR development board. I am using SPI3 on pins 111, 112, and 113. There are pullup resistors to 3.3V on the SCLK line. SPI3_MOSI pin 113 drive the SDIN while SPI3_SCK pin 111 drives the SCLK of the DAC7811. The SYNC signals comes from an I/O Port pin 58 under software control. The SPI interface is programmed for high-level idle state and data samples on first falling edge.

https://old.iar.com/website1/50.0.1.0/581/STM32F407ZG-board-schematic.pdf

I noticed on your scope capture you have 17 clock pulses while the STM32 SPI interface has 16 clock pulses but it met all the DAC7811 timing requirements. What is your clock frequency?

Thanks

I made a mistake on that plot. This the correct one.

The CLK frequency is aprox. 18.3kHz. From your plot I assume that your capture is using a CLK frequency aprox. 5MHz. I took a plot at that frequency as well. Just be aware that the DAC output needs time to transition at large steps. Take a look at the plot below.

How are you injecting the signals to the Evaluation Board? A description of which pins you are using or a picture of your setup will suffice.

I think I found the problem. it appears the DAC7811 is sensitive to signal overshoost and undershoost because of the jumper wires from the the micro to the DAC7811 evaluation board. I have added 200 ohm serial termination resistors to the SCLK and SDIN signals and the DAC is now working properly.

Thanks.