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Clock input frequency versus sampling rate versus output clock of ADS5404 and similar ADCs

Jacob Putz
Intellectual 665 points
Other Parts Discussed in Thread: ADS5404, ADS4149

First of all I would like to have something clarified. Does the input clock determine the sampling frequency (80 MHz clock results in a sampling rate of 80Msps)?

I want to operate the ADS5404 at its maximum sampling rate (500Msps) .  Assuming the above is true, I provide the ADC with a 500MHz LVDS clock.  Since the ADC is a DDR ADC, is it correct to say the Output Clock (DACLK and DBCLK) is half the input frequency (250 MHz)?

  • 0
    TI__Mastermind 29220 points

    Hi,

    For this device your understanding of the clock rates is correct.  You would supply a 500MHz clock to the ADC for a 500Msps sample rate and the DDR LVDS output clock would be 250MHz with a sample on the rising edge of the output clock and a sample on the falling edge.

    Not all data converters are exactly like this, so you would need to check the datasheet carefully.  Some other ADCs might output the LVDS DDR output clock at the full rate of the sample clock and output half the sample on the rising edge and half the sample on the falling edge - essentially pushing the DDR clock rate twice as fast in order to use half as many LVDS outputs (such as ADS4149 for example).  And yet other devices might have a clock divider on the input clock so that the effectve sample rate might be half or a quarter of the clock you give to the ADC.

    But for the ADS5404 i is as you describe.

    Regards,

    Richard P.