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What is minimum clk frequency for DAC904 family?

henning larsen
Intellectual 335 points

Datasheet is a bit unclear when it says: Min update rate of 125MSPS, Typ 165MSPS because does this mean that it is guaranteed to support an update rate of  125MSSPS but typically will support 165MSPS? I guess so, but then the question is: are there a minimum required update rate (<125MSPS)? 

The answer is relevant as we would like to use the device in a sort of bust and hold mode ie. throttling down the update rate periodically. Implicitly this also means that it may not change output when the clock is stopped. Is that the case?

Thanks,

br.

  • 0
    TI__Genius 17340 points

    Hi Henning,

    The 125 MSPS minimum is the minimum guarantee maximum sampling rate. There is no AC coupling on the internal clock path, so you should be able to run it a low as you want.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Intellectual 335 points

    Matt,

    Thanks for the answer.

    If the datasheet should be clear and according to the information you provided - and it should, then the update rate specification ought to have the wording:

    Maximum output update rate: Min 125 MSPS.  

    and not the wording:

    Output update rate: Min 125MSPS

    as this literally says that the rate should be minimum 125 MSPS, which is wrong. Its the maximum rate which is restricted.

    br. henning