Other Parts Discussed in Thread: ADS1672
Hey,
The ADS1672 data sheet mentions a low jitter clock is required to meet the performance specs of the ADS1672 (datasheet, page 22) but the maximum jitter required to meet the ADC performance specs is not listed. What is the maximum jitter required? My application includes a variety of ADC clock rates, from 3.072 MHz at 256x oversampling to 12.288 MHz at 64x oversampling. Does TI have any solutions that can generate this range of clock frequencies and meet the ADC jitter requirements? My main system clock is 10 MHz.
Thanks,
Tobyn