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ADS1278 CLK input

Other Parts Discussed in Thread: ADS1278

Hello,

Does the clock input of the ADS1278 need to have a 50% duty cycle?  Could I instead run it off a clock with a duty cycle of 1/3 or 2/3?  For example, a clock that was high every one out of 3 cycles of a 80MHz clock for a clock rate of 26.67MHz.

Also, I am trying to generate the clock from a Tiva C Launchpad and would appreciate any comments you might have on the following post:

http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/324018.aspx

Regards,

Curtis Mayberry

  • Curtis -

    For the high precision/performance offered by this device, you really want to have a PLL or clock source and not a PWM signal.  PWM will typically vary a little and effectively create a 'jittery' clock, which delta-sigmas tend to handle better than other device; however with the expected high-level of performance, this is definitely not optimal.

  • Hey Greg,

    Thanks for the response, I hope everything is going well in Dallas.  

    The EVM suggests using a crystal oscillator (http://www.ctscorp.com/components/Datasheets/008-0256-0.pdf) with the following jitter performance:

    Period Jitter, Pk-Pk - - - 50 ps
    Period Jitter, RMS - - - 5 ps
    Phase Jitter, RMS - - - 1 ps

    I assume this would be a sufficiently clean clk source.  Is a PLL still necessary?  Would there be any significant ADC performance gain from using a PLL?  I suppose it could still be useful to make the input frequency a bit more flexible

    Is there a good way to predict how the jitter will impact the performance?  Will it effect the SNR directly?

    Keeping in mind that the ADC performance might be impacted, I assume I can still use the PWM signal shown in the other post to continue working on the formware until I can fix the clock source.

    I plan on directly connecting the oscillator to the clock input with just a 50 ohm resistor between.  I assume that the 50 ohm resistor suggested by the datasheet and used on the EVM just acts as a LPF to limit the ringing.  In the EVM they have two other parts on the output of the xco but they just seem to multiplex between the onboard oscillator and an external clock source.

    Also, in the ADS1278 datasheet it suggests that for optimum performance the SCLK needs to be some fraction of the CLK input.  How important is this?  Do you have an idea of how and why this effects performance?  I assume that SCLK and CLK don't need to be synchronized, correct?

    I appreciate the help.

    Thanks,

    Curtis

  • Hello !

    I'm asking myself the same question. If a PLL really needed or a quartz oscillator is enough ? For example, a CMOS compatible oscillator like http://www.mouser.com/ds/2/417/7x-14310.pdf

    Also same question for the synchronisation of the SCLK and the CLK. Has there been any response ?

    Thank you !

    Norman

  • Hi Norman,

    A PLL is not required to drive the CLK input of the ADS1278. A single-ended CMOS crystal oscillator can be used alone.

    Synchronizing the CLK and SCLK signals to some 1/2^n ratio has generally yielded the best SNR performance. However, any other ratio that still meets the required timing specifications will not degrade device performance beyond the electrical characteristics listed in the datasheet.

    Best Regards,