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ADS8568 - Busy Signal does not go low

Other Parts Discussed in Thread: ADS8568

Hi, I'm using the ADS8568 analog to digital converter and interfacing to it using an Altera Cyclone FPGA. After raising the CONVST_x signal, the busy signal goes high and always remains high indefinitely. What could cause that to happen? I'm using the chip in hardware and parallel mode.

  • Hi Jonathan,

    Welcome to the e2e forum! 

    Do you have the RESET pin of the ADS8568 tied to a resource on your FPGA?  I would suggest that you toggle that pin high after your power on your board.  The BUSY output getting stuck may be the result of an incomplete power on reset (POR) due to a glitch on your AVdd rail.  If that does not help your situation, please consider posting a schematic of the ADS8568 area on your board along with screen shots of your digital control inputs.

  • Hi Tom, toggling the reset pin worked and I am getting data from the ADS8568.  Thanks for this fix.


    However I'm encountering another problem.  The input range is very small.  It's suppose to be +/-4Vref = +/-10V but I'm only getting values when the input range is about +/-2V before it starts reporting the full positive or negative scale.  

    Below is my schematic.  Some things to note:  The +12V and -12V routing is switched on the schematic.  They have been corrected with flywires on my PCB.  The capacitors at the bottom of the page each go to an AVDD pin.  The GND and A_GND are tied at the power supplies.

    Thanks for your help.

  • Hi Jonathan,

    Unfortunately the schematic did not come through.  Was the device on your board powered backwards (before the flywire change)?  Can you verify what the reference voltage is?

  • Hi Tom, I noticed the VREFN was not tied to AGND.  When I tied VREF to AGND the problem was solved and I'm now reading the full voltage range.

    Thanks for your help!

    Jonathan

  • Great news Jonathan!

    Thank you for letting us know and please keep us posted on your progress.