ADS1218 - ssi clock

Hi Shubham,

Unfortunately we do not have example code using the TIVA processor at this time.  You should be able to find example code for the TIVA processor elsewhere on TI.COM. 

For the ADS1218 you will need to hold CS low throughout the entire communication transaction, so if you are using CS you will need to use a GPIO pin to control CS and not the SS pin for the TIVA SPI.  The clock polarity and phase will depend on the POL pin setting of the ADS1218.

If you have a more specific question, I can try to answer.

Best regards,
Bob B

Hi Bob ,

Thanks for responding . First and foremost is what clock should i select for spi ?

I am using 4Mhz on Xin  but i suppose that is frequency at which ADC works, is that ryt ?

HI

Thanks for replying . I am trying to read from ADC after initializing it . So i was using this DSYNC command which is used to Synchronizes the ADS1218 to the serial clock edge . Now my POL pin always high . So should i use POL = 1 PH = 1 for slave clock ?. 

Hi Shubham,

Yes that is correct.  When the ADS1218 POL pin is set high, CPOL=1 and CPHA=1 and corresponds to SPI Mode 3.

Best regards,

Bob B

Thanks for confirmation bob yet couple more questions in my gray matter :

1) DSYNC command should be used prior to every read frm adc or only when i change the input channel ?

2) With every read command there is some delay required . how do i calculate that considering i use 1 MHz clock ?

3) What command is used to trigger ADC ,i can't find any specific command which start the operation of transform  at any certain point ?

hi Bob,

Thanks for replying

1)  Yeah i was thinking the same as i m using auto mode so until there is channel change i wont use dsync command

2) Yeah i read that i was just confused that time delay mentioned is with respect to ADC clock or SSI clock .

     but from what i infer from ur reply its the SSI clock isn't it ?

3) This one was little tricky i thought there must be some interrupt or register which commands ADC to start conversion

    but what i understood  is that it will start working as soon as it is in Wake up mode .

Regards

Shubham

Hi Shubham,

All of the tosc timing is based off the inverse of the fosc clock of the ADS1218, which is the master clock for the ADC.  This is determined by the crystal used for the input or external clock provided to the XIN pin.  The SPI serial clock must be at least 1/4 of the master clock frequency for proper operation.

The ADS1218 will start converting after power up as long as the PDWN, RESET and DSYNC pins are logic high.

Best regards,

Bob B

Hi Bob,

Is it neccesary to use Delays ? i can wait for DRDY to go high for reading data .

also i m little confused when i see that timing specification as SPI is full duplex read and write should happen at the same

time so why this delay in Din and Dout ? .

HI Shubham,

The delay is not with respect to the conversion cycles, but rather to the decode time for commands to be interpreted to know which data is required (register, conversion result, etc.) before data is placed into the output register.  Also, there may be a different delay time as it relates to completion of a command, such as RESET or calibration.

With respect to reading out the conversion results, it is best to read the conversion results based on DRDY as you have mentioned.

Best regards,

Bob B

HI Bob,

Truely said but my doubt is specific to my use case . i am using tm4c123bh6zrb chip and here is abstract from its datasheet :

The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely

and is only valid for Master mode devices/operations. This interrupt can be used to indicate when

it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data

and received data complete at exactly the same time, the interrupt can also indicate that read data

is ready immediately, without waiting for the receive FIFO time-out period to complete.

Now if i go with above i will get the EOT when i send the last bit which should be also be the instant of my last received bit but according to timing specification the delay ensure that both didn't happen at the same time .

Plz help on this .

Hi Shubham,

I think you are missing what is happening in the communication.  Please look at the timing diagram of the datasheet.  You must communicate in 8-bit (byte) transfers and not 16 or 32-bit words.  All commands are structured as one byte in length followed by data.  The ADS1218 must be able to decode the command (read register, write register, reset, calibration, etc.) before the device knows which operation is being performed.  The delay is the time between the command and the data.  Also, you cannot use the SS function as it relates to SSI module as total transaction length can vary, and the communcation to the ADS1218 for the total transaction length requires that CS remain low throughout the entire transaction.  So if you use CS on the ADS1218, then you must use a GPIO function of the processor to control CS of the ADS1218 and not the SS function of the SSI module.

Best regards,

Bob B

HI Bob,

I am indeed using GPIO pin for Slave Assert but i m also using End of Transmission Interrupt  which provokes
 when data is shifted out from the chip . Anyways so i was looking at the timing diagram nd what i infer is data

ready interrupt can be used instead of command delay so should i write dont care bits once i received this interrupt ?

and also would this interrupt come after every 24 bit conversion ?

Hi Shubham,

DRDY only signals when a conversion cycle has completed and new conversion data is available to be read from the ADS1218.  This occurs at the data rate selected.  This has nothing to do with the command decode delay that is required between the command byte and the remaining data (either sent or received.)  In this delay period no clocks are sent (quiet period) and is indicated by t6 in the timing diagram.

Best regards,
Bob B

Hi Bob,

Thanks for the detailed description . It gave me brief insight about the procedure . This is the sequence i think ADS follows:

As soon as i keep the PDWN, RESET and DSYNC pins logic high the ADS starts converting data .

After it has converted its first cycle  DRDY goes active low and then i can use RDATA command to read data .

In RDATA command i will send write command and will let the clcok on upto clock t6 .

then i will shut my clock down during t6 and again give clock to read data from slave .

Is it how it works ?

Hi Shubham,

Yes, the PDWN, RESET and DSYNC must be high for the ADS1218 to run conversions.  DRDY will transition from high to low when the conversion is completed.  If you do not read out the conversion resuslts, the next DRDY will actually pulse from low to high to low.

This is assuming that you have either the appropriate crystal connected to the XIN and XOUT pins, or are providing an external clock to the XIN pin.  This clock should always be running otherwise the ADS1218 will not work.  This is the clock that is the master clock for the ADS1218 operation and is called fosc in the datasheet.  The period of this clock is called tosc.  The communication clock (SPI SCLK, or in your case the SSI clock) must be at least 1/4 of the fosc clock in frequency.  So there are two clocks.  One must run continuously and the other is just for clocking the data in/out of the ADS1218.  The t6 time is based on the period (tosc) of the fosc master clock.

So the fosc clock must be runnning all the time (no stops or delays).  The communication sequence is to send the RDATA command (one byte of data clocked through your SSI interface), a wait time where the serial interface communication clock is idle (where the wait time is determined by the period of the master clock, fosc) then the remaining serial communication clocks are issued to read out the data.

This may be your understanding, but I just want to make sure that you have two clocks for the ADS1218.  The device runs from the master clock connected to XIN (or by crystal oscillator with crystal connected to XIN/XOUT pins), and the ADS1218 will not operate at all without this clock.  The communication clock is a seperate clock that is connected to the SCLK pin.  It is this clock that requires a delay between command and data.

Best regards,

Bob B

Hi Bob,

If i want to read only single conversion value at a time is there any way i can contain DRDY interrupt .

Suppose i dont want multiple low-high-low transition on DRDY on every conversion .

ADC complete the first Sampling, transit the DRDY and DRDY hold its state until i have read the data .

is it possible ?

Hi Shubham,

What the DRDY is signaling is the end of conversion/new results posted.  If you have not read the data before the next DRDY transition, you have lost the previous results.  The type of conversion process you are asking for is a single conversion mode, which is available on the ADS1220.  This mode is not available on the ADS1218.

Best regards,

Bob B

Hi Bob,

I tried the ADC Read but couldn't get the correct value .I wrote the code with the following init sequence 

#define SETUP_DATA 0x1E
#define MUX_DATA 0X01000 
#define ACR_DATA 0X00
#define IDAC1_DATA 0X00
#define IDAC2_DATA 0X00
#define ODAC_DATA 0X00
#define DIO_DATA 0X00
#define DIR_DATA 0X00
#define DEC0_DATA 0X80
#define MDEC1_DATA 0X4F
#define OCR0_DATA 0X00
#define OCR1_DATA 0X00
#define OCR2_DATA 0X00
#define FSR0_DATA 0X24
#define FSR1_DATA 0X90 

#define FSR2_DATA 0X67

#define ANALOG_VOLTAGE_MAX 5.0 //  Calculated this using 2VREF/PGA wherein my VRef is 2.5 V , PGA is 1 

#define ANALOG_VOLTAGE_MIN 0.0  // As i want only positive signal negative is AinCOMM which is grounded 

#define FIXED_POINTMAX (0x00FFFFFFUL) // As it is unipolar the max fixed point value

void ADC_Read(adcchannel_t channel,adcbuffer_t *rx_buffer ,uint8_t rx_buffersize)
{
IArg key;

uint8_t tx_buffer = RDATA ;
uint8_t read_buffer[3] = { 0x00, 0x00, 0x00 };
uint32_t analog_read;

key = GateMutexPri_enter( mutex_ADCHandle);

ADC_SelectChannel(channel);

ROM_SysCtlDelay(1000);

Ssi2Xfer(handleADC,&tx_buffer,sizeof(tx_buffer), ADC_DELAY(50), &read_buffer[0], sizeof(read_buffer));

GateMutexPri_leave( mutex_ADCHandle, key);

// converting 24 bits into 1 read cycle

analog_read = 0;
analog_read |= ( read_buffer[0] << 16 ) | ( read_buffer[1] << 8 ) | ( read_buffer[2] );

analog_read &= 0x00FFFFFF;

*rx_buffer =(float)((((float)(analog_read)) / ((float)FIXED_POINTMAX)) * (ANALOG_VOLTAGE_MAX - ANALOG_VOLTAGE_MIN));

}

Any Suggestion ?

Hi Shubham,

Nothing stands out to me as incorrect within your code.  Some additional information that would be helpful is what is the applied voltage at the inputs, what are you expecting as a result, and what is the actual result?  Also scope/logic analyzer shots of the communication would also be helpful.

Best regards,

Bob B

HI Bob,

Something amazing happened now .

ADS1218 returns 0xFF0000 every time i read with different analog value.

With the same code it was working albeit showing wrong values

but today whatever i apply it always return the same .

I checked the registers they are all correctly set ,so must be hardware issue .

Any suggestion ?

HI Shubham,

Can you send me your schematic and scope shots of your communication?

Thanks,

Bob B

Hi Bob ,

I was able to read values correctly from ADC . But i gave delays ,and now i want i to work with DRDY interrupt .

Please suggest changes i should make ?.

So far i can only think DSYNC after init and making DRDY pin as interrupt .

Any further modification is required ?

Hi Shubham,

The biggest factor is using DRDY as a controller interrupt.  As soon as DRDY transitions from high to low, you should read the data as soon as possible.  This data must be read before the next DRDY.

DSYNC restarts the conversion process.  This is usually used to sychronize to an external event, or to synchronize multiple converters.  For the normal continuous conversion process DSYNC does not help much unless there was an input voltage step change relative to a mux input change.  Depending on the digital filter mode selected, you may need to wait for three conversion cycles for the digital filter to fully settle.  Another way to do this is to thow away 3 conversions and keep the fourth (and following) conversion results.

Best regards,

Bob B