Other Parts Discussed in Thread: TMS320F28335, DAC7716EVM, DAC7716
Hello,
I am using the DAC7716EVM and DSP TMS320f28335 for converting DAC by SPI communication. I tried to setup and gave the simple code to the DSP.
The signal from DSP is correct (I see on the oscilloscope), but the output of the DAC is seemly not working (I gave the analog input is +-11V, ref is 5V, digital input is 3.3V).
Can anyone help me to check my code or if someone have the sample code to show me the correct way to communicate this EVM board. Many thanks!!!!
Here my code:
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
void delay_loop(void);
void spi_fifo_init(void);
void InitGpio(void);
void tx_data_dac(Uint16,Uint16);
Uint16 shift_4_bits (Uint16);
void CS(int);
void chanel_0(Uint16,Uint16);
void LDAC(int);
void Reset_DAC(int);
interrupt void spia_txisr(void);
interrupt void spia_rxisr(void);
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
int counter=0;
int i[8];
int count=0;
Uint16 j= 1024;
void main(void)
{
InitSysCtrl();
// InitSpiaGpio();
InitGpio();
// Step 3. Initialize PIE vector table:
// Disable and clear all CPU interrupts
DINT;
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl();
InitPieVectTable();
EALLOW;
PieVectTable.SPITXINTA=&spia_txisr;
PieVectTable.SPIRXINTA=&spia_rxisr;
EDIS;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER6.bit.INTx2 = 1; // TXSPI interrupt
PieCtrlRegs.PIEIER6.bit.INTx1 = 1; // RXSPI interrupt
IER=0x20; // int6 enable
EINT;
ERTM;
// Initialize the SPI only
spi_fifo_init();
// Reset DAC by hardware
Reset_DAC(1);
Reset_DAC(0);
//Latch is not transparent
LDAC(0);
// Loop for transer SPI
while(1) {
if (count==2)
{
// CS(1);
LDAC(1); // open latch to send out voltage
SpiaRegs.SPIFFTX.bit.TXFFIENA = 0;
count = 0;
delay_loop(); // wait a bit before next transmitting
// delay_loop();
LDAC(0); // close latch to wait for next digital input
// CS(0);
SpiaRegs.SPIFFTX.bit.TXFFIENA = 1;
}
}
}
// Some Useful local functions
void delay_loop()
{
long i,j;
for (i = 0; i < 500000; i++) {
// for (j = 0; j < 10; j++) {}
}
}
void spi_fifo_init()
{
// Initialize SPI FIFO registers
SpiaRegs.SPICCR.bit.SPISWRESET = 0; // reset SPI - 0x000F
SpiaRegs.SPICCR.bit.SPILBK = 1; // loop back
SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // clk polarity is falling edge
SpiaRegs.SPICCR.bit.SPICHAR = 11; // data length = 12b (0-->15 means 1 bit to 16bits)
SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0; // disable rx overrun flag bit interrupts (SPISTS.7)
SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Enable normal phase - 0x0002
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // master mode
SpiaRegs.SPICTL.bit.TALK = 1; // enable talk
SpiaRegs.SPICTL.bit.SPIINTENA = 1; // SPI int disable
SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // FIFO transmit enable
SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // re_enable FIFO transmit enable
// SpiaRegs.SPIFFTX.bit.TXFFST = 0xFFFFF; //
SpiaRegs.SPIFFTX.bit.TXFFIENA = 1; // FIFO transmit interrupt
// SpiaRegs.SPIFFTX.bit.TXFFIL = 0x02;
// SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // clr TXFFINT flag in SPIFFTX
//SpiaRegs.SPIFFRX.bit.RXFIFO = 1; // re_enable FIFO receive enable
SpiaRegs.SPIFFRX.bit.RXFFIENA = 1; // FIFO receive interrupt
// SpiaRegs.SPIFFRX.bit.RXFIFORESET= 1;
// SpiaRegs.SPIFFCT.all = 200; // delayed transfer
// SpiaRegs.SPISTS.all=0x0000;
SpiaRegs.SPIBRR= 36; // Baud rate with freq 1Mhz
// SpiaRegs.SPIPRI.all=0x0010;
SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI
}
void InitGpio()
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)
// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA)
// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
/* Configure SPI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SPI functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // Configure pins as GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // control Uni-Bip B
GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; // control Uni-Bip A
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1; // control LDAC pin 17
GpioCtrlRegs.GPADIR.bit.GPIO26 = 1; // control CS pin
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1; // control Reset DAC RST
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; // control Uni-Bip B - clear bit means Bipolar +-
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; // control Uni-Bip A - clear bit means Bipolar +-
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1; // control LDAC - transparent latch
GpioDataRegs.GPASET.bit.GPIO26 = 1; // CS pin active low
GpioDataRegs.GPACLEAR.bit.GPIO27 = 1; // Reset - active low
GpioDataRegs.GPASET.bit.GPIO27 = 1; // Not Reset - active low
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
EDIS;
}
interrupt void spia_txisr(void)
{
count++;
/* if(j<=1280) {j++;}
else
{j=1024;}
chanel_0(j,0); */
//tx_data_dac(0,j);
chanel_0(1200,1100);
SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;
PieCtrlRegs.PIEACK.all |= 0x20; // Group 6
}
interrupt void spia_rxisr(void)
{
SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;
SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1;
PieCtrlRegs.PIEACK.all |= 0x20; // Group 6
}
void tx_data_dac(Uint16 first_half,Uint16 second_half)
{
switch(count)
{
case 1: {SpiaRegs.SPITXBUF = shift_4_bits(first_half); break;}
case 2: {SpiaRegs.SPITXBUF = shift_4_bits(second_half); break;}
}
}
Uint16 shift_4_bits (Uint16 data)
{
data = data<<4;
return data;
}
void chanel_0(Uint16 first_half,Uint16 second_half)
{
if (first_half<1024) {first_half=1024;}
if (first_half>1279) {first_half=1279;}
// first_half = 1024 + first_half;
// if (second_half <256) {second_half=256;}
// if (second_half >3840) {second_half=3840;}
tx_data_dac(first_half,second_half);
}
void CS(int state)
{
if (state|=0)
{
GpioDataRegs.GPACLEAR.bit.GPIO26 = 1; // begin to transmit
}
else
{
GpioDataRegs.GPASET.bit.GPIO26 = 1; // stop to transmit
}
}
void Reset_DAC(int state)
{
if (state|=0)
{
GpioDataRegs.GPACLEAR.bit.GPIO27 = 1; // 1 is Reset
}
else
{
GpioDataRegs.GPASET.bit.GPIO27 = 1; // 0 is Run
}
}
void LDAC(int state)
{
if (state|=0)
{
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1; // LDAC transparent
}
else
{
GpioDataRegs.GPASET.bit.GPIO12 = 1; //
}
}
