• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 412 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About PLL Lock of DAC5688

Satoshi
Guru 19645 points
Other Parts Discussed in Thread: DAC5688

Please let me know below about PLL Lock of DAC5688.

-----------------------------
[Question]

- Please teach me the view of time until VCO is stabilized.
(Since DAC is set up, is putting in the waiting time like which appropriate for TXENABLE?)

- Does time until VCO is stabilized have the influence by temperature?

- Please let me know a means to check operation of VCO.


[Additional information]
It will become unfixed if it operates in order of the following.

Reset
↓
A setup of DAC
↓
10μs wait
↓
TXENABLE=H

However, a normal performance will be carried out if 10μs wait is changed into 10ms wait.
-----------------------------


Thank you for your consideration.

  • 0
    TI__Guru* 78584 points

    Satoshi-san,

    Let me double check on the settling time requirement to the DAC5688 and get back to you.

    You should set the VCO setting per our datasheet recommendation on page 8 of the DAC5688 datasheet. These settings are tested in our production site and should work across temperature.

    -Kang

  • 0 in reply to Kang Hsia
    TI__Guru* 78584 points

    Satoshi-san,

    Once the device is programmed, and the supplies and clocks are stable – the PLL lock time should a function of the loop bandwidth set by the external loop filter.  You’d like to have something like ~10 time constants to be sure everything has completely settled, and with a loop bandwidth of ~100KHz (10uS time constant) – something like 100uS should be safe.

    -Kang