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Clock configuration at DAC34H84 EVM for Xilinx VC707

Maik Hoffmann1
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005

Hello,

I connected the EVM to the VC707 and solved the power problems.

But now I tried to configure the CDCE62005 on the board, but it doesn't work.
I have to use only the VC707 and this EVM. I tried the configuration with the "well" documented Labview program.

I can only use the onboard 19.2 MHz Oscillator. With the Configuration FB: 48, InputDivider: 1, Ref Divider: 1, Prescale 2 I got at the PLL_LOCK a 660 kHz signal with nearlly 60 % duty cycle.
In this configuration the Fvco is / should be 1843.2 MHz. but with output divider 10 I got a frequency of 84.4 MHz instead of 92.16 MHz.

If I use a higer number for R and I, so that the Fcomp will be lower I got no signal at the PLL_LOCK but nearly the same output frequency. Whicht is the right Value for Fcomp?

Using the 19.2 MHz as clock source works fine, but I need a clock configuration of nearly 400 MHz.

Can anybody help me?

  • 0
    TI__Guru* 78884 points

    Marik,

    You may refer to the following post for some discussion on the CDCE62005 in PLL synthesizer mode. There are a few config files supporting various clocking frequencies of the CDCE62005.

    For further support on the configuration of the CDCE62005, please refer to the E2E clocking forum. Thanks.

    -Kang