DAC3482 why is I & Q shifted with same data

Tim,

The possible phase shift between the two channels could be due to the following:

1. if you are using the DAC3482 EVM with default transformer coupled output, then there may be some phase difference between the two transformers. 

2. we had a customer with similar issue before and the problem was due to different memory pointer location for the channel pattern read back (between the two channels: rising and falling edge of DDR) in their FPGA. After they aligned the memory pointer locations for both channels, they were seeing the same aligned data output.

You may try the following:

1. Speed up or slow down the DAC sample rate and see if the output phase shift is constant or not. If the output phase shift is less than a sample difference and maintains similar delay over speed, then the delay may be introduced by the transformer. You may try to terminate the DAC resistively to avoid this. 

2. Depending on your FPGA design, you may try to swap channel I and channel Q location to see if the phase difference tracks the change. For instance, instead of sending channel I on the rising edge of DATACLK, try send it on the falling edge. I understand in theory that both data should be the same, but perhaps that there are some shift introduced during different stages of the design. 

-Kang

As it turns out, the I & Q data were not "identical". 

The same data was being sent to I & Q but it was getting captured by the falling edge

of the clock first (i.e. Q got the data first). 

That makes it obvious why there is a phase shift.