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ADS1281 modulator

Hans-Juergen Nitzpon
Prodigy 10 points

Hi,

according to page 4 of the datasheet, the modulator clock is specified between 1MHz and 4.096 MHz. What is the reason for this lower limit? Is this given by the modulator design or rather by the following decimation filter settings. I am considering using only the modulator and doing the decimation by the DSP. Would it be possible to clock the modulator below 1 MHz or should I rather use a software sample rate converter/decimator to obtain decimated sample rates below 250 sps?

Thanks for your advice

Hans

 

  • 0
    TI__Guru* 97835 points

    I believe that the lower limit is specified at 1MHz because the operation was characterized there.

    While I don't think there will be a failure to operate with a lower frequency, there is at least one other reason to keep the clock frequency higher. Since the input is chopped, there is a risk that the noise will go up. As the frequency of the chopping goes down, more of the flicker noise will be in band.

    For lower data rates, I think the best thing would be operate it with the standard fclk=4.096MHz and either throw away the data you don't need or don't read it out.

    Joseph Wu