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The question about DAC5688

Satoshi
Guru 19685 points

Other Parts Discussed in Thread: DAC5688

Please let me know three points below about operation of DAC5688.

------------------------------------------------------------------------------------------------------

- Interpolation is used.
If it sees with a synchroscope from the input of data to an output, it will be delayed for about 4.4 μs.
Then, please let me know exact delay time.
(Is there any application note which calculates delay time?)
----------------
Specification of operation
CLK2=200MHz
NCO=50MHz
Interpolation=x4
----------------

 

- Does SNR change by the case where it does not use with the case where internal VCO is used?
(Is SNR improved if internal VCO is turned OFF?)

 

- While inputting fixed data into DAC and checking the output, whenever it reswitches on a power supply and does a setup of DAC again, the outputs of DAC differ.

if it is checking with the spectrum analyzer,an output with 3 patterns.
(What kind of output, its under a check)

Was there such any example in the past?

Specification is the following.
--------------------
20MHzInput
Sampling: 80x4Msps
Interpolation=x4
output: x2
--------------------


------------------------------------------------------------------------------------------------------

Thank you for your consideration.

  • 0
    TI__Guru* 83515 points

    Satoshi-san,

    1. The digital latency spec on page 6 of datasheet shows the overall latency in DACCLK cycles. For 4x interpolation, the latency is 276 clock cycles. NCO adds about 24 clock cycles (i.e subtracting 8x interpolation with NCO with 8x interpolation without NCO to get 24 clock cycles). The total latency is about 300 clock cycles. With 200MHz of DACCLK, I expect 1.5us. 4.4us may be too much. The customer may send a single pulse at the MSB input and check the output pulse at the output to measure latency. 

    2. The internal VCO/PLL will add additional noise to the output when compared to the external clock mode. You can see the difference from the WCDMA plots from Figure 11 to Figure 18.

    3. the FIFO and NCO may need to be initialized again upon power up. Use the initialization signal programmed in config22 and config23 to initialize the logics to double check. 

    -Kang

  • 0 in reply to Kang Hsia
    Guru 19685 points

    Dear Kang-san

    Thank you for the advice.
    Moreover, there was a question by addition about SFDR from a customer.
    Please look at the following.


    ------------------------------------------------------------------------------------------------
    ・Is In-Band of the datasheet10 page figure5 "In-Band SFDR vs Intermediate Frequency" above the characteristic when the late frequency of 10MHz～40MHz is outputted?
    Fig.6: Is Out-Of-Band of "Out-Of-Band SFDR vs Intermediate Frequency" the characteristic when 40MHz～330MHz is outputted?
    ⇒Is customer less than SFDR 65dBc in 76MHz～95Mz made into the object?

    ・By the standard of a product, spurious needs to be 70dB or less.
    75dB or less is aimed at as ability.
    However, since it becomes the following spec., please teach me how to improve.

    <<phenomenon >>
    ・FPGA -> DAC5688 -> transformer
    ・Transmit by data rate 155.648MHz between FPGA-DAC5688.
    It interpolation(s) x4 in DAC5688 inside, and is 622.592MHz.
    If it sets up so that it may be set to Fout=76MHz at Nco, spurious of the following will be set to around 70 dB independently [ 76MHz ].

    79.648MHz : FS(622.592MHz)/4-76MHz
    228MHz    : 76MHz * 3
    231.647900MHz : FS(622.592MHz)/4+76MHz
    235.296000MHz : FS(622.592MHz)/2-76MHz
    242.592000MHz : FS(622.592MHz)-5*76MHz
    380.000000MHz : 76MHz * 5
    387.296000MHz : FS(622.592MHz)/2-76MHz

    Since application is FM-related, 79.648 MHz near a career of exteriors Low Pass Filter cannot be used.
    (Others can connect the exterior LPF)
    Moreover, Fout is changed into below.
    Fout 86MHz    spurious -- 69.648 MHz
    Fout 95MHz    spurious -- 69.648 MHz

    ⇒It will be set to 155.648 MHz if Fout and spurious frequency are added.
    (76MHz + 79.648MHz = 155.648MHz)(86MHz + 69.648MHz = 155.648MHz)(95MHz + 60.648MHz = 155.648MHz)

    As mentioned above, I think that there is a cause after NCO.
    (Reason: The frequency of the 80dB, and 155MHz circumference changes spurious, and the preset value of NCO removed FIR1～FIR2)

    Is this dependent on the spec of SFDR?
    Or are there any improvement proposals (ex, between FPGA->DAC5688 is made late)?

    ------------------------------------------------------------------------------------------------

    Best Regards,

    Satoshi

     

  • 0 in reply to Satoshi
    Guru 19685 points

    Waveform information came to hand about the contents asked the other day.
    I think that it attached and if something becomes a hint of cause unfolding.

    Please let me know about the corrective strategy of SFDR asked the other day.

    Best regards,

    Satoshi0753.Spurious_waveform.xlsx

  • 0 in reply to Satoshi
    TI__Guru* 83515 points

    Satoshi-san,

    I have received additional information via email. I will review the additional data and correspond offline via email. 

    -Kang