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DAC+FPGA+ADC (ADC12J4000)

Other Parts Discussed in Thread: ADC12J4000EVM, ADC12J4000

Hi,

I am looking for a low cost DAC+FPGA+ADC setup which can sample/generate at at least 2GSPS with 12 bits. Of the available ADCs, I found ADC12J4000EVM. I know it can be used with the TSW14J56EVM, but the page mentions that the maximum speed is 10.3Gbps only. Is there another setup I can use?

Also, can I get the NPR graph for the ADC12J4000 chip?

Thanks!

  • Hi Rosanah

    The ADC12J4000 device can sample at rates from 1 to 4 GSPS, and outputs serial data at rates up 10 Gbit/sec (2.5 x DEVCLK).

    In the raw 12 bit ADC data mode the output is on 8 serial lanes at 2x the input DEVCLK.

    In the DDC (Digital Down Converter) modes the output is on 1 to 5 serial lanes at rates of 1x, 1.25x, 2x or 2.5x of the input DEVCLK (sampling clock) depending on the selected decimation and output framing. Therefore the TSW14J56 is suitable to support this device at the highest sampling rates.

    Preliminary NPR data at 4GSPS is shown below (red, green and blue are for 3 measurements at each power level of the same device):

    Best regards,

    Jim B

  • So I am trying to measure a signal and its distortion products which occupy the frequency range from 5MHz-1GHz. I should be able to do this directly using the ADC12J4000 and TSW14J56 ? I will not be demodulating or downconverting.

  • Hi,

    In the raw 12 bit ADC mode, is the serial bitrate 2xDEVCLK for EACH of the 8 serial lanes?

    Thanks!

    Rosanah

  • Hi Rosanah

    Yes, in raw 12 bit (also known as DDC Bypass or Decimate by 1 mode) the serial output is on 8 lanes at 2x DEVCLK.

    Below is a table summarizing the lane parameters for all modes. The right-most column shows the output rate as a function of input DEVCLK.

    Best regards,

    Jim B