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ADS1230 clock problem

Akmal Habib
Prodigy 10 points
Other Parts Discussed in Thread: ADS1230

Hi All

I am using ads1230 with open AINP and AINN . But it is not giving any data on DRDY/DOUT pin on clock of 125HZ. But when I use clcok from evaluation board which is of 

2MHZ then it gives some output i.e it is working. My question is, is there any ristriction on clock frequency? its datasheet is not giving any information on clock frequency.

datasheet just talks about rising and falling edges. Please help me out in this regard.

Thanks in advance

 

Best Regards

Muhammad Akmal 

 

  • 0
    TI__Prodigy 115 points

    Hi Muhammad,

    I assume that you are referring to an SCLK frequency of 125Hz. At an SCLK frequency of 125Hz, you are unable to complete data transfer within a single sample. Since the ADS1230 will update the output register at the end of each conversion, you will see corruption of data when operating at that speed. At 10 samples per second, you would need to run at least 250Hz on SCLK and at 80SPS you would need run at least 2kHz. However, I don't recommend operating this slow since you run a greater risk of corruption if data cannot be transferred out in time. Is it possible for you to operate with a higher SCLK in your application? One other thing to remember is that if the SCLK bus line is held constant for 64 conversions, the bus will timeout and reset communications.

    If you are referring to the system (modulator clock), the minimum external clock frequency (fclkin) is listed at the bottom of page 3 as 200KHz.

    Best regards,

    Mike Beckman