• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 956 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC 7568 simultaneous Output update sequence

Embedded Solutions
Intellectual 390 points
Other Parts Discussed in Thread: DAC7568

Hi all,


I have problem with DAC7568 converter. I want to use simultaneous dac output update mode with LDAC pin. Converter is connected to OMAPL137 and it works in synchronous mode. I was trying to load DAC output registers and than make high to low transistion on LDAC pin but without any change on DAC output. Do I have to perform any additional steps in init ? Where can be the problem?


Sourece code:

https://github.com/kyak/microdaq_ert/blob/master/blocks/mdaq/dac7568.c

Thanks!

  • 0
    TI__Genius 10615 points

    Hi,

    LDAC cannot be reconfigured to ignore the HIGH to LOW transitions. The DAC outputs will update on the falling edge of LDAC.

    Can you share some details of your application?

    What are you trying to accomplish with this LDAC HIGH to LOW transition? Maybe I can try to give you some ideas to get around this.

  • 0 in reply to Eugenio Mejia
    Intellectual 390 points

    Hi,

    I just want to use simultanious mode. In my case falling edge doesn't cause update of DAC outputs. Can you provide proper command sequence to update outputs in simultanious mode or C code example ?

    Thanks!

  • 0 in reply to Embedded Solutions
    TI__Genius 10615 points

    Hi,

    There are 2 possible ways of accomplishing a simultaneous update on all the channels.

    1. Hardware LDAC
    2. Software LDAC

    I do not have any example C code that I can share with you, but I can explain the command sequence.

    Hardware LDAC sequence:

    Initial States:

    SCLK = X

    DIN = X

    /SYNC = HIGH

    /LDAC = HIGH

    /CLR = HIGH

    Sequence:

    1. /SYNC goes LOW
    2. Write only (DIN latched in on the falling edges of SCLK)
      1. Format: 0x00[Channel][Data]00
      2. [Channel] 4 bits
      3. [Data] 12 bits
    3. /SYNC goes HIGH
    4. Repeat for 1-3 for all channels.
    5. LDAC goes LOW (DAC output updates)
    6. LDAC goes HIGH

    Take a look at table 35 for all the sequences.

    Software LDAC Sequence:

    The write sequence is the same as the HW LDAC, but LDAC is tied LOW at all times and there is an extra frame which updates all the DACS (0x01F00000)

    Take a look at table 35 in the datasheet for more options.

    Hopefully this helps.

    If you are still experiencing issues, just let me take a look at some scope captures. This may help me check if the sequencing is correct.

  • 0 in reply to Eugenio Mejia
    Intellectual 390 points

    Thanks to explanation, DAC works as expected.

    Regards Grzegorz