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AFE7225 DAC

Chen Yang
Prodigy 10 points

Hello,

I'm in trouble with 7225, and I can hardly find out what's wrong.

I'm sure I can configure 7225 through SPI, because ADC frame clock was observed.

But, the dac always stay at mid code, whatever I do.

So, could you please help me?

  • 0
    TI__Genius 9695 points

    Hi Chen,

    The DAC's output is mid code when it is shut off. This may be due to anyone of the following:

    -Register 0x103 is set to 0x01 which powers down the transmit signal signal chain through SPI

    -The DAC clocks (CLKINP and DAC_DCLKIN) are not set up properly which can cause a FIFO collision to occur.

    Refer to table 10-2 of datasheet for the relationship between CLKINP, DAC_DCLKIN and interpolation factor.

    -There is no clock at DAC_DCCLKIN.

    If you are not able to resolve the issue after confirming the above 3 conditions, provide details of your setup: clock frequencies, interpolation and register settings so I can help further.

    Thanks,

    Eben.