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ADC128S102 reading problem when switching between channels

Harry Song
Intellectual 360 points

Just found the problem of this ADC. When switching between channels, if the voltage is quite different, it will cause the wrong result.

for example, connect Ch4 to 1.6V, connect Ch7 to 3.3V, and reference is 3.3V, if continuously reading either Ch4 or Ch7, the result will be good, Ch4 is about 0x800, and Ch7 is around 0xfff, but if you read ch4, ch7, ch4, ch7....

the result for ch4 will become 0xaa5, while ch7 is still 0xfff.

  • 0
    TI__Expert 3325 points

    Hi Harry,

    At the center of you problem is the fact that the internal sampling capacitor is not discharged between samples. In essence the sample acquired from Ch4 is still there when acquiring Ch7. You have to give the sampling capacitor enough time to settle between samples.

    Here a couple of approaches you can take:

    • extend the Track period - Track is the only time when the sampling capacitor is connected to the source. This can be easily done in the FPGA (slow the SCLK during Track), but not so easy with the uC.
    • slow down the SCLK for the whole SPI transaction
    • reduce the impedance of the source driving the input channel
    • double sample the channel and discard the first sample

    Hope this helps,

    Sincerely,

    tom  

  • 0 in reply to Tom Domanski24
    Prodigy 10 points
    I had the same problem. I slowed down the SCLK frequency and it got better.
    Thank you very much!