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Problem reading Dual channel ADS62P49 in DDR LVDS. Seems SDR?

PGil
Prodigy 70 points
Other Parts Discussed in Thread: ADS62P49

Hi,

I'm using an ADS62P49 with a virtex 6. But unfortunately the DDR LVDS bus doesn't seem to be good. MY SPI is OK to read and write the Register.

Here is my problem. My LVDS Bus seems in SDR mode.

I always read the even bit on the bus.   Even on the scope I see this behavior.

Note: My FPGA sampling seems ok because when I use the clock pattern I have no glitch. My Sample period is 100MHz as a starting point.

Here is What I'm doing.

1. reset the chip.

2. configure the chip: here is my config.

    int regAddress[18] = {0x20,0x3F,0x40,0x41,0x44,0x50,0x51,0x52,0x53,0x55,0x57,0x62,0x63,0x66,0x68,0x6A,0x75,0x76};
         int regValue[18] = {0x04,0x20,0x08,0x80,0x00,0x46,0x00,0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x00,0x03,0x00};

3. Read the data in chipscope. And check with a scope the DATAclock and D0-D1 LVDS pair. My LVDS clock Vpp is 376mv seems ok .

4. When I use custom pattern set at 0x0001 I expect to get a Clock pattern on the D0-D1 pair But I see a constant 1.

5. When I use custom pattern set to 0x0002 I expect to get another clock patter on D0-D1 But I get a constant 0.

6. This behavior is valid for all my bit.

 

So Can you help me to find my Odd Bits of the LVDS BUS?

 

Thank you.

 

 

 

 

 

  • 0
    TI__Expert 3865 points

    Hello,

    can you please provide the relevant portion of the schematic? I'd like to take a look at the configuration pins. If you don't want to post it on this forum you can email me directly at tneu@ti.com.

    Best regards,

    Thomas Neu

  • 0 in reply to Thomas Neu
    Prodigy 70 points

    Hi,

     

    Thank you for your fast answer.

     

    My ctrl[1-3] pins are tie to ground and SPI pin is connected to 2.5 to 1.8 voltage translator.

     

    My schematic is coming on your email.

     

    After some test, I realized that when I reduce my clock speed, The ADC began to run correctly. I will try to give it a better clock(noise, jitter, Duty cycle). To see if it works better.

     

    Does a "bad" clock can produce this problem?

  • 0 in reply to PGil
    Prodigy 70 points

    HI all,

     

    This issue is now fixed, After some test I found that the bit "Low Speed Mode" was responsible of the behavior. Putting the ADC in High speed mode, even if I run just below 100MHz, fixed the problem. 

     

    Thank you.