DAC8581 tUPDAC timing

Hello Mark,

This device in NRND (Not Recommended for New Designs.) Therefore we would suggest not using it. Why is this device appealing to your application?

Mark J Medrud said:

a. On the first page of the data sheet, under Features, "3-MSPS Update Rate" is claimed.  This would appear to be a nominal/rounding of 50MHz(max) SCK divided by 16.

     b. The Timing Requirements on p5 above Figure 1, gives a tUPDAC of 1us(min).

There are 2 ways to look at this:

1. The fastest you can possible write to the DAC digital interface.
   1. This is how fast the digital input interface can write values to the DAC.
   2. The DAC output may not have enough time to settle when updating at this rate.
   3. This rate may be desired in order to have a smoother (although delayed) output voltage, since the DAC output never truly settles at this rate.
2. The fastest rate that will allow you to write, update and settle the DAC to ½ LSB.
   1. This value allows the DAC to settle to about ½ LSB before a new digital sequence is started.
   2. This rate may be desired in order to get a quantized output voltage.

Usually the first method is the one specified in datasheets.

As you mentioned the first page features a 3MSPS update rate.

Take a look at Figure 1 in the DAC8581 datasheet. Using the first definition, the timing would be calculated using:

• tLEAD (20ns)
• 16*SCK (16*20ns)
• tWAIT (100ns).

Notice that tLEAD overlaps with the first CLK cycle, so the tLEAD contribution is actually just 10ns.

The calculation becomes 1/(10ns + 16*20ns + 100ns) = 2.33MSPS.

This is still below the 3MSPS detailed in the datasheet, this is most likely because it does not consider the tWAIT specification.

If you are interested in calculating the second method, you would indeed use the tUPDAC as well as the settling time of the device. If you are interested in the settling time specification you can take a look at the following blog post: DAC Essentials: Understanding your DAC's speed limit

If you need me to explain anything else, please do not hesitate to ask.

     Thanks for your help!

     Unfortunately, I specified the DAC8581 last December when the (then current) data sheet listed it as Active.  Oh, well...these things happen.

     Mainly, I need bipolar output, but the price is also critical.  The alternate part suggested on the ti website is nearly 3 times as expensive, as are all of the other bipolar-out candidates I've found.

     If it's not practical to use the DAC8581, I'll have to re-spec a unipolar part, plus a board spin.  I already have a dual op amp on the board as a quasi-differential output buffer.  Add 3 more resistors and a unipolar DAC will do.

     I see that there is significant 'factory stock' in reels claimed by at least one disti--although my boss resists lifetime buys.  Who should I contact to find out if an End Of Life or Last Buy date has been set for the DAC8581?

     I guess what I should have asked is, "What's going on internally during tUPDAC."

     Can I assume that it covers some internal analog process--and that it has nothing to do with the data latching from the shift register into the DAC register at the 16th SCLK fall?

     If I understand your comments correctly, then starting a new SPI transaction after tWAIT will not destroy the current sample until the next 16th SCLK fall.  This application will have no step-wise output changes and a microsecond or two of lag is not important.

Thanks again, Mark

Hi Mark,

It isn't necessarily impractical for you to use the DAC8581, we've just noticed some process shift over the lifetime of the part that can cause some issues in certain configurations. We are working with our final test team to implement a screen at final test to ensure that the issue doesn't make it to the field any longer, but it has not been completed yet. We can try to access whether it's practical for you to use the DAC8581 if you can share a schematic (either on the forum or we can take this offline to email) and share what performance parameters are most important to you.

As of right now there is no plan to NRND the DAC8581. Since we noticed the process shift we have simply marked it not recommended for new design. For the foreseeable future you do not need to worry about making a lifetime buy.

The timing diagrams are not always to-scale. So despite how the illustration looks t_UPDAC is actually much longer than t_WAIT. t_WAIT is expressing the time it takes for the digital interface to decode the input command, apply the new data to the corresponding register, and cause the appropriate action to begin to take place. It's what I labeled as "dead time" in the blog post Eugenio linked you. Violating t_WAIT could create issues with the digital interface (of course, there is margin built into this spec so you might be able to take a few parts into the lab, violate it, and see no issue). As long as you wait t_WAIT after the 16th falling SCLK edge your word will latch to the DAC data register.

t_UPDAC is an odd specification to be present in this table, it's not something we would normally include in a digital timing table. This is the settling time specification of the device which matches the settling time to 0.003% FSR specification in the electrical characteristics table for an 8-V step. This includes the dead time, slew time, recovery time, and linear settling time. It really should be listed as a "typical" value though instead of a minimum since if we were to make a smaller step on the output the settling time would be much less than 1us since we cut out the entirety of the slew region.

     Thanks so much for your (and Eugenio's) help--very illuminating.

     I have attached a partial schematic, but it may not tell you much by itself.  The board is intended for one product as-is, with additional circuitry to validate the DAC8581 at its highest practical sample rate.  It has digital power and ground planes plus an analog ground plane.  There is also a layer to distribute the various other supply and reference voltages.

     There are two DAC8581s.  The first one (in the schematic), and another with its output connected only to test points.  Both get their data from a Microchip dsPIC33EP.

     Logic in a CPLD stretches the dsPIC's Frame Synch pulse so that it can be used as the DAC's CSn.  This is so the DAC can be fed from a block of DMA RAM, minimizing processor overhead.

     The 1st DAC's output is scaled to +/-2.5V quasi-differential to drive a voice-coil servo controller.  500ksps is sufficient for that function.

     The 2nd DAC is for experimentation.  I'm hoping to clock it at 50MHz, transmitting 3 bytes per sample.  The first 2 bytes are the sample data.  The 3rd is not clocked into the DAC and its transmission time covers tTD, tWAIT, and then some.  An anti-imaging filter will come later.  The hope is to add a dual purpose programmable voltage output and low-cost arbitrary waveform generator feature to a future product.

     I guess the most important parameter is INL for the first DAC, which is adequate based on the DAC8581's spec sheet.  For the second DAC, sample rate is most important--though more bottom-up.  At this price, we'll take whatever we can reliably get from the part.

Thanks again, Mark