TSW1400 EVM capture event and USER_LED interpretation

Venky,

i am not 100% clear on what you are asking for. Is there a problem with your board? If so, what ADC EVM are you using? Can you provide more info on your setup. Below is an explanation of the status LED's.

Regards,

Jim  

USER_LED0 and LED1 indicate transmission of data samples over SPI interface.

USER_LED2 turns off when the FPGA is in reset mode.

USER_LED3 indicates the FPGA PLL1 is locked to the ADC input clock from port 0.

USER_LED4 indicates the FPGA PLL2 is locked to the ADC input clock from port 1 or locked to the

FPGACLK from the DAC when in the DAC mode.

USER_LED5 indicates that the DDR memory initialization is complete and the interface is ready to use.

USER_LED6 and LED7 indicate that the two SPI FIFO’s are empty.

Jim,

There is no issue with the board I need this information for my custom algorithm on PC.

Let me rephrase the question.

1.What is the estimated time  when the following command is issued on PC to when the capture actually begins on FPGA?

Time 1

calllib('HSDCProAutomation_64Bit','Pass_Capture_Event',TimeoutInMs);

Capture begin on TSW1400 firmware

Time 2

In other words, what is Time2 - Time1?(Actual / Estimate)

2. Does any LED indicate the actual capture event on TSW1400 ?

The sampling rate used is Fs 16.368 MHz.

thanks

Venky

Venky,

Please send me your email address and I will pass it on to a group that can possibly help you with this question.

Regards

Jim, 

venkatesh.viswanathan@commscope.com

Hi Jim,

Any update on my question ?

I started receiving mails from other forums but on different topics.

thanks

Venky