ADS1271 - Frame sync serial interface, start-up problems

Are you driving the FORMAT pin from processor or are they hardware configured?

If SCLK and FSYNC behave as outputs, it may be that you are inadvertantly floating the FORMAT, which puts the device in Modulator Out mode where SCLK and FSYNC are outputs.

You also want to per a sync operation after changing the FORMAT pin (see datasheet page 29, Format Selection section)

First of all thank you for your fast reply.

- The FORMAT pin is driven from a processor pin, but the pin has an internal pull-up which is active from the start-up. We already checked this issue by adding an additional pull-up with 2.2kOhms.

- In our case the FORMAT pin isn't floating. We are using the ADS1271 and not the ADS1271B. According to the datasheet the output modulator mode is only available with the ADS1271B (see page 5, Terminal Functions).

- The FORMAT pin is stable a Hi-Level from the beginning. But we also tried to do a sync operation as you mentioned with no change of the situation.

In my opinion the datasheet of the ADS1271 does not reflect the complete behaviour of the ADS1271 in the frame sync serial mode:

1. Page 5, Terminal Functions: SCLK Digital Input <<< WRONG: SCLK is Digital Input/Output
2. Page 5, Terminal Functions: FORMAT=1, then FSYNC is input <<< WRONG: FSYNC is Digital Input/Output
3. Page25, Section "SCLK (SPI Format)":
   "... For the fSCLK/fCLKratio of 1, care must be observed that these signals are not tied together. After Power On, SCLK remains an output until a few clocks have been received on the CLK input. ..."
   
   <<<< But what about frame sync serial mode? There is nothing mentioned about this and this is exactly the behaviour we have in our application.
   

Is there anything else we have to take care of?

In our case the CLK signal is generated by the processor. That means we get the CLK signal after the processor is initialized and the application program is running. CLK and SCLK are tied together (fclk=fsclk=225kHz).

Your comment is highly appreciated.

The Frame-Sync mode is SLAVE only.  Frame Synce MASTER mode is not support with this device.  The user must supply FSYNC and SCLK, therefore they are both inputs.

Regarding information on Frame-Sync mode, have you noted the information beginning on page 26?  Information on most of page 25 pertains to SPI mode (just to clarify).

You may want to also make sure that the timing delay between the SCLK and data lines is not too large since you could potentially end up with corrupted data.  Also note the FSYNC to CLK requirements on page 26, to avoid invalid data readback.

We know the Frame-Sync is Slave only and that we have to supply FSYNC and SCLK. That's the reason why we use processor output pins.

We also know the about the information on page 25 and 26 and that the information pertains to SPI mode or Frame-Sync mode respectively.

The assumption that SCLK is an input led us to use one clock signal for SCLK and CLK of the ADS1271. So we tied SCLK and CLK together. A processor pin of the internal synchronous interface is driving the clock signal continuously.

The only problem we have is that the SCLK behaves as an output after power-up even though FORMAT=1 (pull-up). After a few clock cycles SCLK becomes an input. But this means that SCLK and the processor clock pin having a "fight" at power-up.

Please check this out: Use an ADS1271 with FORMAT=1 and check SCLK being input or output after power-up.
 We know that the datasheet has no information about this, anyway please check it.