I am interfacing an ADS6424EVM with a Xilinx ML605 development board over FMC (using a TI adapter). Can anyone provide any references or code to accomplish this?
Thank you.
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I am interfacing an ADS6424EVM with a Xilinx ML605 development board over FMC (using a TI adapter). Can anyone provide any references or code to accomplish this?
Thank you.
Hi,
We do not have reference code for the ML605 or the many other FPGA development platforms from the various FPGA vendors.
Regards,
Richard P.
Thanks for the response, Richard.
I am aware there is no support specific for my goal, but is there perhaps something you can offer that could be of some educational value to me? Code used on the evaluation platforms would be useful.
Hi,
What we *have* been providing is the Verilog source for our TSW1200 Capture Card when asked. If you can provide me with an email address then I can sent that to you. I didn't offer that up at first as it is not simply drop-in code for your platform. But it is for Xilinx anyway. The TSW1200 uses a Virtex4 FPGA and the Verilog code uses the Xilinx IDELAY element to adjust timing into the IDDR elements. You would have to determine the correct tap settings for the IDELAY in the Virtex5 to make this same approach work as it would be different than for Virtex4. And you would have to remap the pin assignments in the constraint file to account for the different pinout. And - the TSW1200 code was not really written for public distribution, it is a bit short on documentation..
Regards,
Richard P.
That would be great.
Please send the files to samerhawayek at gmail dot com
Thanks in advance, Richard.
Hi,
Please provide an email address that I may email the source code to.
and what ADC device part number will you be using? when you append to a previous E2E posting I can only assume you would be using the same device, but there are two sets of source code for the TSW1200 depending on the device type you would be using.
Regards,
Richard P.