Hi, we have an ADS1234 customer having the following issue...
We are experiencing an output from the ADC that, when analyzed, is out of the expected range (as seen by the uController). This unexpected reading forces the uController to shut down the heated zones and reports an error to the system. We have monitored the inputs to the ADC and can see no strange noise spikes or any shift in the signal during the period just before the shutdown occurs. Next we monitored the voltage entering directly into the ADC conversion stage across the filter capacitor located on pins 9 to 10 of the IC. We did this using differential inputs to the scope. We could now see each of the analog signals from the output of the PGA as they entered into the ADC for conversion. Again, the signals were clean and were not at any unexpected levels which would have put it outside the expected range, and thus would have produced the trigger.
Our experience with film capacitors of the nature mentioned in the Appendix A of SBAU120B, is that if improperly treated when installing (overheating or improper soldering technique) then they can be very noisy. Thus, our first step was to change this capacitor for a known good one that was properly and carefully installed. Upon inspection, we found that many of the capacitors that we had in stock showed cracks across the multilayered exposed sides of the chip BEFORE installation. Since we believed that might be an issue, we ordered more from various manufacturers and with both 2% and 5% tolerances (to broaden the selection we could obtain). We still could find only a few that were without cracks before installation.
My question mainly is with the characteristics of this capacitor. Why was film chosen? I assume it was for time/temperature stability of the value. Are there other characteristics that would prevent the use of an NPO/COG ceramic of the 0.1uF value? Such as a Murata GRM31C5C1E104GA1L or a TDK C3225COG1H104J?
Most of these issues with the capacitor have been largely dismissed, at the moment, as we have not been able to prevent the failures regardless of the capacitor on the board (especially with the ceramic cap as mentioned above). Our signals appear very clean and stable at the ADC input. Thus, we are looking at other issues especially with the timing and the SCLK levels. We are using the POWERDOWN signal to initiate the conversion process for each of the 4 inputs to the ADC. Since we are using 2 of these ADCs, we are monitoring both DRDY/DOUT with an interrupt routine. When either goes low, the routine waits for the 2nd to go low before initiating a read out with the SCLK signal.
We are continuing to explore the signals and capture them as a failure occurs.
We appreciate and suggestions/help you can give us.
