• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 46 subscribers
  • Views 467 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

High Speed Data Converter Pro "JESD IP Core_LaneSync"

David Hand
Intellectual 915 points
Other Parts Discussed in Thread: ADS42JB69

I'm using the TSW14J56EVM with a ADS32JB69EVM. When I select the ADS42JB69_LMF_421 and then look at the "Dynamic Configuration" dialog, there is an item "JESD IP Core_LaneSync" parameter that is set to 1. What is that parameter for? All the others make sense.

  • 0
    TI__Genius 9695 points

    Hi David,

    If you have access to the user's guide for the MTI JESD204B IP, the "JESD IP Core_LaneSync" parameter writes to register 0x34. This register determines whether lane synchronization is enabled or disabled. This affects the rules used for character replacement defined in the JESD204B standard.

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Intellectual 915 points

    Eben,

    Thanks, that explains it. I'm trying to use the Altera JESD204B megacore (so far with no luck), but it has similar registers (offset 0x50). It defaults to enabled, so I guess that's not the problem.

    Thanks,
    Dave

  • 0 in reply to David Hand
    TI__Genius 9695 points

    Dave,

    If you are not already doing this, you have to invert the dev_sync_n signal from the altera Megacore IP to the ADS42JB69.

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Intellectual 915 points

    Eben,

    I was pretty sure that was true, but it is very helpful to have it confirmed. I guess it saves power to not always drive the line.

    My problem is that dev_sync_n never seems to change. In SignalTap, it just stays 0 no matter what I do. I'm not sure I have the reset sequence correct, but if anything, I would think it would be 1 (ie deasserted). It's like it is not even attempting to do a synchronization.

    I got a Tx core to drive a DAC with no problem. Not sure what bit of magic I'm missing for the ADC side.

    Also, it seems like I should be using rx_dev_sync_n, but that signal does not exist when you generate an Rx+Phy core (as opposed to Tx+Rx+Phy).

    Thanks,
    Dave

  • 0 in reply to David Hand
    TI__Genius 9695 points

    Dave,

    A few things to try:

    -Probe the output of the 8B10B decoders to verify if the ADC is sending 0xBC to the FPGA on all the active lanes with dev_sync_n low. If it is not sending 0xBC, push the hardware reset (SW1) on the ADC and use the GUI to re-program the ADC again

    -Verify that sysref is connected to the RX core in the FPGA and there is a clock running on the sysref pin.

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Intellectual 915 points

    Eben,

    That was an extremely helpful suggestion! It let me see what was going on and I now have sine waves after 2 weeks of banging my head against the wall. I'm new to the Quartus II tools (about 3 weeks) and did not realize I could look at signals inside their cores.

    Thanks,
    Dave