problem communicating with ADS1248 with Arduino

Hi Johan,

I don't see anything in your schematic that would prevent communication.  Before communication can take place, the device must be powered, the RESET pin must be high, and the START pin must be high.  There is also a wait period after power up before attempting to communicate.  This time is given in the datasheet.

The SPI is Mode 1.  SCLK should dwell low, with data changing on the rising edge of SCLK and stable (read) at the falling edge.  Data is transferred in bytes, but make sure CS is low throughout the entire communication transaction.  For example reading data by command (RDATA) is a 4 byte transaction.  The first byte is the command followed by 3 bytes of data.  CS must remain low throughout the entire time and must not toggle within the byte frames.

Can you send scope/logic analyzer shots of the communication?

Best regards,

Bob B

Dear Bob,

Thanks for the reply!

Since the output pin voltage on Arduino is +5V I've changed DVDD to +5V (correct?).

I don't quite see why I need these "PULL_UP" and "PULL_DOWN" resistors on CS, Start and Reset?

What would be the interesting pins to look at in a scope? I can only access 4 pins simultaneously. DRDY, DIN, DOUT and SCLK?

Kind regards, Johan

On my PCB manufactured according to previously attached schematics I'm not able to pulldown the voltage on the CS-pin to more than 4V when the ADS1248 is soldered to the PCB.

Does this imply that there is something broken in the chip?

Regards, Johan

Hi Johan,

It is not required to have pullups or pulldowns on the pins you mentioned, but having these resistors does allow the ADS1248 to power up in a known state while the controller is initializing.  The ADS1248 will not function if the RESET pin is low, so the controller connection to this pin must be set to logic high.  The START pin is like a power down pin, so for the ADS1248 to convert, or to read/write the registers, the ADS1248 needs to be powered up which means that this pin must be logic high.

As there are two ADS1248 devices on your board, you will need to use CS to communicate to these devices separately.  Again, using the pullups will keep the devices from accidently driving the DOUT pins at the same time on power up.  The primary pins to monitor with a scope are CS, SCLK, DIN and DOUT.  You can look at DRDY to verify the device is functioning.  If START (and RESET) is high then you can check to see if the part is active by monitoring the DRDY line with the scope to make sure the DRDY pulses at the default data rate (5sps or every 200ms).

If you cannot drive CS low, then you cannot communicate to the part.  Do you see the issue with both ADS1248 devices?  First you might recheck the layout to make sure that the footprint matches correctly for the ADS1248.  The CS pin is a CMOS input pin with some ESD protection circuitry.  If the ESD structure is damaged, then you might see an issue.  This could have happened if the Absolute Maximum Ratings were exceeded.  One way where the Absolute Maximums could be exceeded is by initially powering your digital with 3.3V while attempting to control the ADS1248 with 5V.  This would force the ESD diodes into conduction.  Long term excessive current will damage the ESD cell.  So it is possible that the device was damaged if this condition occurred. 

Best regards,
Bob B

Dear Bob.

Thank you so much for your help. Indeed you've pinpointed my source of error to my faulty parts. I'll put on new converters and try to monitor the pins you suggested.

Kind regards, Johan

Hi Bob.

I've put on new ADS1248-chips and now the communication works. I retrieve data with the "recieve data once" command and my only problem is that I don't know how to utilize the DRDY-signal. Reading from the datasheet I don't need to wait for a DRDY_low to send the recieve data once (and recieve result).

Do I only need to wait for DRDY_low if I use the recieve data continously-command?

Kind regards, Johan

Hi Bob.

Thanks for your answer.

Is there a "startup"-time or "settling"-time for the RDATAC-command? Since I use two ADS1248 to retrieve my results I must keep track on which converter is sending DRDY and the only way to do that on a single DRDY-line is to stop one of the ADC's to send DRDY pulse. (Is DRDY-signals stopped when SDATAC-command is issued?)

Also I'm a bit concerned about the stability of my results. When I do readings I get anything within  +-0.05 degrees C (I use 4-way measurement setup). Any thought on what this big fluctuation be due to?

I will add linear regulators on AVDD and AVSS do mitigate any noise from my PC PSU (switched). Is there any point in adding linear regulators also on digital supply voltage?

Could the fluctuation of the results be due to the dynamic range of the ADC? Since I use 4-way measurement setup I measure from about 100 ohm to 140 ohm. Would there be a point for me to use a 3-way measurement with compensation so that I measure 0 ohm to 40 ohm instead?

Thankful for fast reply!

Kind regards, Johan

Hi again Bob,

One additional question. If I use linear regulators do generate a +2.5 V and -2.5 V AVDD respectively AVSS is it wise to tie the AVSS to gnd with decoupling caps (100 nF)?

/Johan

Hi Johan,

When issuing the RDATAC command, the command takes effect on the next completion of conversion (DRDY transitioning low).  Keep in mind that with the START pin high, the ADS1248 is always converting (or continously converting).  What the RDATAC mode does (which is the default startup mode) is to automatically place the conversion results in the output register so you can read the results directly without issuing a command (RDATA).  In other words all you need to do in RDATAC mode is send 3 bytes worth of SCLK and retrieve the data sent out DOUT.

Sending the SDATAC command will stop the automatic posting of results to the output register.  It does not stop conversions and the SDATAC command has no effect on DRDY.  When the SDATAC command is issued, the current conversion taking place will be posted automatically and the next conversion following the SDATAC command will actually be in the SDATAC mode.  So, the conversion that is taking place will be in RDATAC mode and when it finishes the next conversion will be in SDATAC mode.

Here is a concern I see and that is with tying the DRDY pins together.  These are output pins that are always active (they do not tri-state with CS).  You will have output driver contention when connecting these pins together.  If you want to connect the pins to a single input then you must do so with logic devices (AND, NAND, OR, NOR, etc.).  If you use an external clock source, you can keep both devices sychronized by having each ADS1248 using the same clock source.  The START pin can be used to synchronize the conversions.

Regarding the supplies, the PSRR is pretty good so it is unlikely you will see much benefit by further regulating the DVDD supply.  It is always a good idea to place decoupling caps near the device supply input pins.  This would include AVSS to AGND when using bipolar supplies.

Noise is always a concern with respect to precision measurements.  The difficulty is in finding the source of the noise.  Without knowing the noise source it is difficult to know what to do to limit the noise.  Also, when adding devices to compensate for the input range you can actually make the situation worse.  Any added resistance in the input path will add noise and stability issues (drift) that can affect the total error of the measurement.  I would stay with the 4-wire RTD as this should provide the best overall measurment if you follow the information in SBAA201 (http://www.ti.com/litv/pdf/sbaa201).

Best regards,

Bob B

Hi Bob.

Ok. So could I just skip the DRDY-channel and tie Dout together and use the combined Dout/DRDY-function?

It seems to work for me to read and write register with this setup but when I retrieve data there seems to be some issue. I read in the datasheet that when CS is high the chip shouldn't react to any SPI-commands and also Dout has high impedance. I believe I should be able to put only one CS low and send RDATA command and retrieve result from selected chip without conflict with the other chip.

I'm really greatfull for your help.

Regards, Johan

Hi Johan,

To use the combined function of DOUT/DRDY you must set the IDAC0 register bit 3 high.  When using the DRDY only signal, the pin is always active (never goes into tri-state) whereas the DOUT/DRDY signal will tri-state when CS goes high.  So unless CS is low, you will never recognize that DOUT/DRDY has transitioned low.  If you use CS and poll the DOUT/DRDY pin, you should use a pull-up on this pin so the signal line is never in an undertermined state.

One other thing to note about DRDY.  Whether you CS or not, any SCLK clock seen on the ADS1248 input will drive the DRDY pin high.  The logic that drives the state of the pin is totally independent of the SPI bus.  For the DOUT/DRDY pin, following the read of data you may have to send a NOP to force the DOUT/DRDY pin back high if you use a polling method.

Best regards,

Bob B

Hi Bob.

After I do the reading with CS still low I send the NOP-command to toggle DOUT/DRDY high. After NOP-command I set CS high and chose another chip.

My question is: When I want to read from the first chip again do I need to send NOP-command again before reading? Or do the chip remember that I've already sent it and I can read the DOUT/DRDY output and start to read the data directly if signal is low?

Kind regards, Johan

Dear Joseph,

Thanks for your quick reply.

I do not use logic to combine the signal. I just tie them together and use a pull up on that line.
 I believe this should be ok since the DOUT/DRDY-signal enters a high impedance state when CS is high.

My thought is to:

1. Set CS low

2. Send RDATAC

3. send NOP to set DOUT/DRDY-signal high

4. Wait untill DOUT/DRDY turns low

5. Retrieve results

6. Send SDATAC

7. Set CS high

and then same procedure for the next chip.

This seems to work but my problem now is that the results I receive are corrupt.

Maybe 3 out of 5 retrieved results are reasonable whilst the other look something like 111111000000  or 1000. I am considering if this is due to noisy digital signal. Any thought on what this may derive from?

If it is a noisy digital line that corrupts the results it is strange that all my read- and write- register commands always works flawlessly.

Also this error does not occur when I increase the data rate to 80SPS (compared to my normal operation at 20SPS).

I'll try to look at the signals in an oscilloscope.

Thanks for your support!

Kind regards, Johan

Johan,


Looking at your method, it generally looks correct to me. I don't see any obvious problems with the way that you have it set up.

For the noise problem, I think it would be best to see a scope shot of the communications. If you have some sort of logic analyzer to check communications, that would help as well.

I'm not sure what kind problem you're having, but you might be able to test to see if it is noise if you change your DRDY MODE bit to 1. That would force the DOUT/DRDY high upon receiving 24 SCLKs. If there is noise then you would see the DOUT/DRDY go high most times when there is an error.

Another thing that you might try would be to add some capacitance from SCLK to GND to clean up this line. If you do have noise, the SCLK line would be the most sensitive.

I will say that I don't think it's noise. I find it unlikely that you would have any difference in readout performance between the 80 SPS to the 20 SPS, especially if the data were being clocked out at the same rate. I would suspect that there might be a coding or communication error that might cause this problem. Regardless, an oscilloscope shot or logic analyzer data would be a great help in debug.


Joseph Wu

Hello,

Here's a screen shoot of the communication. DIN and SCLK are measured close to the chip and CS and DOUT are measured close to the controller. The offset voltage shown on CS1 is incorrect. The signal indeed varies between 0V and 5V.

I send a RDATAC command followed by a NOP to pull DOUT high (I've set the DRDY MODE bit to 1).

So I believe I should have only 0 on DOUT when I send the RDATAC-command? Do I need to empty the register before I send the RDATAC-command?

Clearly I'm doing something wrong. What are you thought on how noisy these lines are?

thanks for your support!

/Johan

Hi,

As I wrote earlier I do not use the DRDY-line to check if conversion is ready. I've tied DOUT/DRDY together of my two chips and set the DRDY MODE bit to 1 for both devices.

In that case I guess it would be like this at startup:

1. Issue SDATAC

2. Immediately issue NOP to pull DOUT/DRDY high

3. wait for DOUT/DRDY to go low

4. send 3xNOP:s to empty register.

Is this correct?

Regards, Johan

Johan,

Yes, that  is correct.

The concern that I had was that in the datasheet, it says that the SDATAC takes effect after the next /DRDY. I wanted to make sure that the output register was completely cleared.

Joseph Wu

Hello,

I never managed to get the converters to communicate correctly with the DOUT/DRDY signals combined. Instead I re-routed separate DRDY-signals for the two chips I'm using and readout the results with interrupts.

This now seems to work as (some of) the results seems reasonable. But I still have issues with the results. Actually the only trustworthy results I can measure is the AVDD and the DVDD voltages. Here I consistently measure 4.8V respectively 5.1V which is also what I measure with my multimeter. Everything else is just off.

E.g. I set IDAC current to be 1mA and I measure arout 0.88mA with my multimeter. R_ref voltage is 2.1V and I measure 1.8V with the chip. With the inboard temperature sensor I read a temperature of 42 degrees in the chip when I use it in room temperature. With 4-wire RTD measurments my readout varies +-5 degrees between result readouts.

Another question: the MSB in the result readout is the sign, right? Is 0 positive and 1 negative?

To you have any thought on what these problems might derive from? I have build everything in an old PSU from a PC. Do you think the PCU could cause these problems?

Thank you!

/Johan

Johan,


I'm glad you were able to get some usable data out.

Starting with the IDAC current, I would note that the initial error is only 6% max. I will say that you are further off from that value, but consider these things. First make sure that the IDAC output isn't forced high in voltage. There can be a reduction in current compliance when the output current is driven high in voltage above 4.3V (assuming AVDD=5V). Another thing to look for is other current leakage paths from the IDAC output. If there are ESD or TVS diodes on those pins, they may have a current leakage. Also consider the possible error of the meter that you are using.

However, I noticed that if you are using the 2k resistor through the IDAC as the reference and you are getting 2.1V, then your IDAC current is 1.05mA. Let me know if I've confused your explanation of what you are doing.

If you're using the internal temperature sensor, the note that it's not guaranteed. However, I've looked as some of the original characterization and final test data, and the error is about 2C for a single standard deviation. If your internal temperature sensor is reading 42C, that seems a bit high for room temperature.

For the data format, the ADS1248 uses a two's complement notation. In that respect, an MSB of 1 will indicate a negative number, but the remaining numbers still follow two's compliment. There's a discussion in the datasheet on page 35, including Table 17 explaining the output.

When it comes to the PSU, I assume that you are referring to using a power supply from an old PC. I've never tried it, but it is certainly possible that it might be noisy and it could throw off enough EMI to create problems. Any switched supply might cause problems with digital lines because of the instantaneous current needed in digital circuits. Generally some sort of LDO might smooth some of the noise, but I'd be very careful about the noise you might get from this setup.


Joseph Wu

Johan,


I'm glad you were able to get some usable data out.

Starting with the IDAC current, I would note that the initial error is only 6% max. I will say that you are further off from that value, but consider these things. First make sure that the IDAC output isn't forced high in voltage. There can be a reduction in current compliance when the output current is driven high in voltage above 4.3V (assuming AVDD=5V). Another thing to look for is other current leakage paths from the IDAC output. If there are ESD or TVS diodes on those pins, they may have a current leakage. Also consider the possible error of the meter that you are using.

However, I noticed that if you are using the 2k resistor through the IDAC as the reference and you are getting 2.1V, then your IDAC current is 1.05mA. Let me know if I've confused your explanation of what you are doing.

If you're using the internal temperature sensor, the note that it's not guaranteed. However, I've looked as some of the original characterization and final test data, and the error is about 2C for a single standard deviation. If your internal temperature sensor is reading 42C, that seems a bit high for room temperature.

For the data format, the ADS1248 uses a two's complement notation. In that respect, an MSB of 1 will indicate a negative number, but the remaining numbers still follow two's compliment. There's a discussion in the datasheet on page 35, including Table 17 explaining the output.

When it comes to the PSU, I assume that you are referring to using a power supply from an old PC. I've never tried it, but it is certainly possible that it might be noisy and it could throw off enough EMI to create problems. Any switched supply might cause problems with digital lines because of the instantaneous current needed in digital circuits. Generally some sort of LDO might smooth some of the noise, but I'd be very careful about the noise you might get from this setup.


Joseph Wu

Hi,

I indeed use 5V AVDD and 0V AVSS. Even though my schematics says that I use 2k res. for reference I actually DO use 2k4. Something is funky here.

After some more measurements on my board I've noticed that the AVDD sinks to 4V when I turn the internal reference voltage on (VREFCON:01). Any thoughts on why this happens? Do I have to change the AD-converters? Are they broken?

When I measure VREF_out with the reference turned on I measure 2.045V respectively 2.048V from the two AD:s.

Kind regards, Johan

Joseph,

 One thing I came to think about is how the internal reference should be routed in the ref. mux. As I previously wrote I measure 2.1V between REFP0 and REFN0. Maybe this voltage is the internal reference and not the IDAC over R_ref? I need internal reference to be on for IDAC but it shouldn't be connected to REF0 input pair, right? If this is the case this would also explain why my voltage drops when I turn on internal reference. I use a variable voltage regulator for my power supply and the output voltage is set by a voltage divider. My guess is that turning on the internal reference in the ADacs connects either VREFOUT or REFPX to the AVDD (somehos). From VREFOUT and REFPX there are two 2k4 resistances (one for each chip) connected to GND that alters the voltage divider.

The voltage regulator anyway doesn't get warm. The reason I use these regulators for the board is that I want to mitigate any power supply ripple that my switched PSU might generate.

I have tried to use an other power supply with well regulated and clean voltage but all my data read problems still remains (but maybe not the voltage drop). I'm really clueless on what might be the problem here.

When I do "normal measurements" I typically read results in one region when the DR is set to 5,10 or 20 SPS and then my reading s mystically change into another level when I use 40,80 or 160 SPS. I notice in table 7 on page 25 that input current changes also between these data rates. Could this give a clue to what is wrong?

Maybe if I give some more examples, numbers and explanations of my problems you might be able to point me in the right direction?

Kind regards, Johan

Johan,


Sorry I missed your last post, I was out last Friday and didn't see this one.

I'm not sure if the voltage is part of the internal reference, but you can test that can't you? Change the value coming out of the IDAC and see if there's a corresponding change with the reference voltage.

If your measurements change with the data rate, there may be quite few reasons for it. If you continue to post descriptions and examples, I'll continue to try to help. Just try to be specific and detailed about the experiments you've tried and the results.


Joseph Wu

Joseph,

Here is the setup and some measurement results attached. These results makes no sense to me.

• MUX0 - 0x01
• VBIAS - 0x00
• MUX1 - 0x20
• IDAC1 - 0x89

Same as before AVDD drops from around 5V to 4.02V when internal reference is turned on.

Joseph,

So indeed the voltage drop was the problem. I find this a bit odd sine the power supply is supposed to source 1.5 A at 5V. What is the approximate power consumption for the analog part? I find on page 2 in the data sheet that the maximum input current is 0.1A.

For the first time I'm now able to do measurements! Many thanks for your kind help.

Kind regards, Johan