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Integral nonlinearity ADS1672

reto hermann
Intellectual 720 points
Other Parts Discussed in Thread: ADS1672, THS4521, THS4520

Hi,

I have measured the linearity error of the ADS1672 in our application circuit and have observed an error that is much higher than it is specified in the DS. Here is the schematicm including the analog Input buffer and the result of the measurement:

0755.ADS1672.pdf

Can you please review the schematic. Any idea what I'm doing wrong ?

Thanks for your answer!

Best regards

Reto

 

  • 0
    TI__Mastermind 23235 points

    Reto -

    What is the source for the reference voltage (don't necessarily need specifics)?  A reference IC or other?  A good reference is required for good performance.

    What is the source of the CLK signal to the ADC?  Crystal/oscillator or processor?

    Additionally, there could be items in your layout:

    - check to make sure the CLK and VREF signals aren't running in parallel as much as possible to prevent coupling of the clock onto VREF.  With them being close to each other, it is hard to avoid.  You can reference the layout on the EVM (in the user guide) for an example.

  • 0 in reply to Greg Hupp
    Intellectual 720 points

    Hello Greg,

    thank you for your reply. Regarding your questions:

    - Reference voltage: We are using a REF5030 (Details see attachment below)

    - The clock source is a 40 MHz crystal oscillator that is connected to an FPGA. The FPGA divides that clock input by 2 using a simple register (no PLL)

    - Layout: The CLK and VREF Signal are not routed in parallel, they do not even cross each other

    In the meantime I have made some additional tests and I have the impression that the error depends on the capacitor value of the capacitor that is connected to AINx:

    4762.reference.pdf

    If it possible that the buffer (THS4521) is too slow ?

    Regards

    Reto

  • 0 in reply to reto hermann
    TI__Mastermind 23235 points

    Reto -

    Thanks for the information.

    The reference appears to be in order.

    The divider on the FPGA clock is probably OK, but be aware that due to the high performance nature of the device, there is sensitivity to jitter and duty cycle.  So non-idealities introduced by the divider can affect your performance.

    It is possible you may get performance with the THS4520; this is the device that we include on the EVM/reference board.  Due to the high sample rate of the ADC, it is critical that the buffer be able to settle the input completely during the sample time of the converter.