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ADS1218 Digital I/O Interface

Other Parts Discussed in Thread: ADS1218

Hi,

I am using an ADS1218 with 5V separate digital and analog power supplies, 4 layers PCB with ground plane. The SPI is connected to a TI microcontroller. The firmware engineer wrote a short test program to set the I/O as outputs (apart from D6 which is an input), i.e 0x40 in register 0x07, and then it switches the outputs high an low (0x55 and then 0xAA in register 0x06). The system does not work as expected and thus I need some help:

1) At the beginning, after ADS1218 reset, thes outputs seem switching correctly, but they switch right after the clock first rising edge following the instruction. POL is hard wired to GND. Is this behaviour right? I would expect the outputs to switch after last falling edge of the instruction (0x56 0x00 0xXX where XX is 55 or AA).

2) After a while, ADS1218 seems to miss a byte and the outputs are quite wrong. I think that the digital waverforms that I enclose explain better than words.

Trace, ADS1218 pin name

D0,  \RESET

D1,  \PDWN

D2,  \CS

D3,  SCK

D4,  DIN

D5,  D0

D6,  D1

D7,  D2

CH1, 5V DVDD

The first picture shows good start and then irregularity after about 10 output cycles 

The second picture shows output switching after next rising edge of SCK

The third picture shows a really strange behaviour where D0 (trace D5) does not switch, D1 (tarce D6) has a delayed transition and D2 (trace D7) switches at rising edge of SCK. 

Thank you for any help you could give me.

Best regards

Roberto

  • Hi Roberto,

    Welcome to the forum!  I have a couple of questions.  What are your register settings?  And what is the master clock frequency (fosc)? 

    I've attached some logic anaylizer shots of what I would typically expect.  There is about a 3us delay after the last falling edge of SCLK and the change of data on the GPIO output.

    Best regards,

    Bob B

  • Hi Bob,

    thanks for your answer. Comparing my results with the surely correct waveforms that you posted was helpful. I think that I found the bug. The testing program does not manage \DSYNC, which is left at low level. Apparently, the ADS1218 does not communicate well on the SPI when \DSYNC is low. This happens with any fosc between 500kHz and about 5 MHz, while the content of the registers is unpredictable because you can't read them back. I hardwired \DSYNC to high level and now the SPI works well and the D0-D7 outputs switch properly at any fosc. It's a pity that I did not find any hint on the ds, I would have saved a long time.

    Thanks again.

    Rgds.

    Roberto 

  • Hi Roberto,

    I'm sorry that you found this out the hard way.  The operation of the DSYNC pin held high is not directly stated in the datasheet because when the DSYNC pin is held low, the device holds the modulator in a reset condition.  As the ADS1218 is primarily an ADC, holding DSYNC low is not normal operation as you will never get a conversion result this way.  The digital circuitry is constantly looking for the rising edge of DSYNC to release the modulator and this will have a priority in the state machine over communication. 

    I can't speak for the author of the datasheet, but the operation is implied by the purpose of the device so there is no need to speak of it in the datasheet directly.  You can see from the timing diagram on page 10 of the datasheet where RESET, DSYNC and PDWN are normally high when operating, with a low condition changing the device operation.  What is difficult when writing these datasheets is to think outside the realm of the design and purpose of the device and think of all the conditions and variety of ways the device may be used.  In other words, you discovered a mode of operation that had never been tried/tested.  Thanks for your diligence in finding the problem and posting the cause.  Hopefully this post will help someone else in the future if they run into a similar problem.

    Best regards,

    Bob B