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TSW1200 VHDL Code

richard fawley
Prodigy 10 points
Other Parts Discussed in Thread: ADS5400

Hi,

Could you please provide the VHDL code for the TSW1200 EVM board  - i have an ADS5400 board and intend to interface @ 1Gsps. My understanding is that this is achieved using dual bus mode each bus using IDDR clocked from an Fs/4 clock provided by the ADC. Question: How is the non-deterministic start-up clock phase issue dealt with?

email to send files: rfawley@teledyne.com

Many Thanks

  • 0
    TI__Mastermind 29220 points

    Hi,

    Verilog code sent to the address provided.

    With the TSW1200 capture card (and our newer capture cards TSW1400 adn TSW1405 which have replaced the TSW1200) there is no issue with the start up of the DDR bit clock since the capture card isonly capturing data from one EVM and one ADC.  The data is always in sequence, and there is no particular requirement that a capture start at exactly one particular sample - so there is no concern about the particular phase of the DDR bit clocks.   If there were *two* ADCs that were to have data captured that needed to be kept synchronized, then the sync or reset input would need to be applied to both ADCs at exactly the same sample clock rising edge to make sure the clock dividers of both ADCs were both reset to the same starting position at the same time.  But for one ADC, there is no ambiguity as to the order of the samples that are captured using the DDR bit clock for the two busses.

    The TSW1200 used dual bus mode for operating the ADC at 1Gsps because the memory blocks in the FPGA had a hard limit of 250MHz operation, so i have to store four samples at a time.  Dual bus DDR makes it easy to get 4 samples at a time to push into the memory.  It would have been possible (in theory) to run the EVM in single bus mode into the TSW1200 at 500MHz DDR and then internally cut the rate down by two again to push four samples at a time into the memory.  But we didnt do that.  The TSW1400 capture card can accept either dual bus or single bus mode of operation.

    Regards,

    Richard P.