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Question About ADS1120 characteristics

Go
Genius 4220 points
Other Parts Discussed in Thread: ADS1120

Hi,

I got some questions about ADS1120 characteristics as follows,

1. Seen in the Figure 39. Simplified PGA Diagram,

   CR buffer (200ohm+25pF) are placed at each inputs of PGA.

   these CR buffer are placed after the internal MUX, right?

2. Is there any data of on resistance of Internal MUX?

3. About the Output data rate described in P26,

    There is the comment as follows 

    "The values provided are in terms of tCLK cycles using an external clock with a

    clock frequency of fCLK = 4.096 MHz. "

    Will the Conversion Times change when using the internal oscillator?

   Is the value of internal oscillator also 4.096MHz ?

Thanks,

Go

 

  • 0
    TI__Guru** 113765 points

    Hi Go,

    See my answers below in RED.

    Best regards,

    Bob B

    Go said:

    Hi,

    I got some questions about ADS1120 characteristics as follows,

    1. Seen in the Figure 39. Simplified PGA Diagram,

       CR buffer (200ohm+25pF) are placed at each inputs of PGA.

       these CR buffer are placed after the internal MUX, right?

    BB> Yes, the EMI filter is placed just before the PGA input after the MUX.  This EMI filter has a primary purpose of reducing the noise within the IC itself.

    2. Is there any data of on resistance of Internal MUX?

    BB> The MUX resistance is a design parameter and will vary with supply voltage, input voltage, operating temperature and lot variation.  The nominal resistance will be around 400 ohms with a 2.7V supply, and will lower as the supply increases.  Worst case scenario is around 2.2k ohms.  You cannot use this value to truly calculate the filter response of the EMI filter in front of the PGA as it varies so much.  Also due to the trace length between the MUX and the PGA, additional noise within the IC may be added by antenna effect.  So the only real values you can count on for EMI filter are the values given in the block of 200 ohms and 25pF.

    3. About the Output data rate described in P26,

        There is the comment as follows 

        "The values provided are in terms of tCLK cycles using an external clock with a

        clock frequency of fCLK = 4.096 MHz. "

        Will the Conversion Times change when using the internal oscillator?

       Is the value of internal oscillator also 4.096MHz ?

    BB> The nominal internal timing relates the same as the external oscillator frequency of 4.096MHz so all conversion times apply for the conversion rates given in the datasheet using the internal oscillator.  What can change is the internal oscillator frequency based on the Electrical Characteristics shown in the datasheet.  If the oscillator is slightly faster or slower than the nominal, the conversion times and digital filter response will change in relationship to the oscillator.

    Thanks,

    Go