Other Parts Discussed in Thread: ADS1602
I would like to use a 40 MHz FPGA clock to drive an ADS1602, a 16-bit 2.5 MSPS ADC, and I'm trying to learn more about how the clock jitter would affect the accuracy of the signal. I need 16 bits to cover the full dynamic range of our signal, but only need about 1% accuracy. 1% of 16 bits requires about 7 bits; In other words, what I really want is a 7 bit floating point ADC with a dynamic range of 9 bits (I'm assuming that there is no sign bit).
Note that the highest possible 7-bit number, 128, would then be at -54 dB of the full scale of 65536.
The datasheet specifies that for a -2 dB signal, clock jitter has to be less than 3.8 ps, and for a -20 dB signal, less than 28 ps. If I assume the scale between -2dB and -20 dB continues to -50 dB, I extrapolate that at approximately -50 dBs, the allowable jitter would be 1100 ps, or 1.1 ns. Is this likely correct, that 1.1 ns jitter would give us values accurate to the least significant 7 bits over the full dynamic range, or how can I determine the limit?
