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Checkpoints for giga sampling ADC application like ADC12J4000

David Park
Expert 6680 points
Other Parts Discussed in Thread: ADC12J4000

When customer use a number of giga sampling ADC, how many they can adopt it in one board? Is there any limitation?

When make daughter card with ADC module, what problem is expected for many daughter card?(loss, signal radiation, etc)

  • 0
    TI__Mastermind 44680 points

    Hi David

    The ADC12J4000 ADC has a high speed serial JESD204B data output interface. In raw 12 bit (DDC Bypass) mode, this interface requires 8 serial pairs. When the DDC modes are used, the output interface requires 1 to 5 serial pairs, dependent on the decimation factor and data rate mode used.

    The number of ADCs per FPGA will depend on the number of available JESD204B compatible high speed serial receivers on the target FPGA.

    The FMC (FPGA Mezzanine Card) aka VITA 57 standard interface is used in our evaluation tools and by many industry vendors making high speed data capture/source boards and mezzanine (daughter) cards.

    http://en.wikipedia.org/wiki/FMC_%E2%80%93_FPGA_Mezzanine_Card

    This standard supports up to 10 high speed serial RX and 10 high speed serial TX pairs. There are no significant problems with signal loss or EMI, etc. caused by using this type of carrier/mezzanine card solution, and it provides a lot of flexibility compared to a dedicated single board design.

    Best regards,

    Jim B