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ADS1248 SPI Communication / RREG Problem

Bryon Palmer
Prodigy 30 points
Other Parts Discussed in Thread: ADS1248

Hello, I'm working on a project using an ADS1248.  The application is for reading four three-wire RTDs, but the issue I'm having is with writing/reading the configuration registers (having even attempted the conversion yet).

I'm relatively new to SPI communication and am hoping I've missed a detail somewhere.  

The issue is that when I read back from a configuration register to check that the data was written, the value returned by the ADS1248 has had the least significant bit truncated (shifted one bit to the right).  For example, if I write 0x70 (0b01110000) to SYS0 using WREG, when I use RREG to read it back I get 0x38 (0b00111000) back.  The phenomenon repeats with every register for any value written (0b00000001 becomes 0b00000000, 0b00110100 becomes 0b00011010, etc...).

Any idea what's going on here?  Clearly I am communicating with the device, I just can't figure what's happening to the least significant bit.

Thanks.

Here's the psuedo code if it helps:

START HIGH

RESET HIGH, LOW, HIGH

DIN: 0x23, 0x00   //RREG command for SYS0

DOUT: Ignore

DIN: 0xff             //NOP command, read SYS0

DOUT: Get 0x00 (expected)

DIN: 0x43, 0x00, 0x70    //WREG for SYS0 with 0x70 (0b01110000)

DOUT: Ignore

DIN: 0x23, 0x00   //RREG command for SYS0

DOUT: Ignore

DIN: 0xff             //NOP command, read SYS0

DOUT: Get 0x38 (0b00111000)    //Not expected, data shifted one bit right

RESET HIGH, LOW, HIGH

DIN: 0x23, 0x00   //RREG command for SYS0

DOUT: Ignore

DIN: 0xff             //NOP command, read SYS0

DOUT: Get 0x00 (expected)

  • 0
    TI__Guru* 98145 points

    Bryon,

    Like most questions about the interface, it would help to have a scope shot to show what you're getting on the device. I'd certainly try to plot /CS, SCLK, and DIN.

    The first thing I'd check is the flavor of SPI that you have the master programmed to communicate. The SCLK dwells low and the DIN is clocked on the falling edge if clock signal. If the master is expecting the data to be on the rising edge of the clock, then you might see this type of a bitshift.

    Again, a scope shot would be the most helpful.



    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 30 points

    Don't have access to a scope, but your suggestion was on the money, I was clocking on the rising edge instead of the falling edge -- all working now.

    Thanks!