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DAC5682Z Configuration

Kyle Yang
Prodigy 40 points

Hi,

I am trying to configure the PLL with m = 3 or 6 with n = 2 using CONFIG9 register. However, it seems like the PLL only supports binary number of 1,2,4,8,16,32. Is it possible to go around with this problem? I've tried to program with m = 3 and 6 and I was able to lock the PLL by checking config0. Is the PLL actually in a weird state?

Thanks

-Kyle

  • TI__Genius 17460 points

    Hi Kyle,

    Only binary dividers are supported. If you program M divider to "3" it's actually a divider of 4. The PLL may still lock but it won't be the frequency you expect. See the CONFIG9 description in the datasheet for details.

    You'll need to use a different reference frequency and make use of the available divider options to generate your desired DACCLK.

    Regards,
    Matt Guibord