Interfacing of ADS54rf63 with Xillinx virtex -6 ML605

Hi,

I think you would do best getting support from your FPGA vendor for things like creating the constraint file and the use of the design tools from that vendor.  When it comes to making the support tools like our capture cards such as the TSW1400 we also are customers of the FPGA vendor and look to them for support for the design tools.

The Xilinx that you are using does provide cells that make it easy to interface to the digital sample bus from the ADS54RF63.  The FPGA provides an input dual data rate (IDDR) cell to latch the sample data on rising and falling edges of the DDR bit clock.  And the FPGA provides delay elements (IDELAY) that can be set to have a particular default delay setting in your design to meet timing setup adn hold times into the IDDR cell.  I am attaching a sketch of how this was done into the Virtex4 of our TSW1200 capture card.    But our virtex4 design would not simply porrt over to your Virtex6.  The IDELAY tap settings would be different and you would need to use the Xilinx Static Timing Analysis tools to find the proper IDELAY settings to meet timing requirements into your Virtex6.  And our TSW1200 was designed under an old version of their ISE tools that are no longer supported - so everything has changed since we did that design. You would need to come up to speed on the new design tools and look to them for support on the tools and on creation of the timng constraints.

But in general, you would look to the ADS54RF63 datasheet timiing numbers for the output data and use that to create timing constaints for your FPGA to describe the input timing to the FPGA.  Then use the STA Static Timing Analysis tools to determine if you meet timing into the IDDR cells.   And for the pin location constraints, you would have to carefully trace through the signal traces and connector pin assingments from the ADC all the way through to the FPGA to find out which signals arrive at which FPGA pins and then tell the design tool what the pin locations are.

Regards,

Richard P.