ADC08D1520

Hi Dan

Q1) To maintain rated performance the ADC should be re-calibrated after making changes to the FSR settings. If very small adjustments to the FSR register setting (In ECM aka extended control mode) are made then the performance will not degrade significantly. If the FSR pin setting is changed between the LOW and HIGH setting or vice-versa, the change is significant enough that the linearity and distortion performance will noticeably suffer.

Q2) Correct. Both the /ECE (active low Extended Control Enable) pin and the DRST_SEL (DCLK Reset Select) pin must be held high in order to use pin 14 FSR as the Full Scale Range select input.

Regards,

Jim B

Hi Jim,

If the input signal into the ADC08D1520 goes outside the dynamic range, say above ~860mV and clips, is the ADC necessarily sampling a "clipped" voltage at the 860mV level? If the input signal is a sine wave, will some samples register 0V when the peak is above 860mV?

Thanks,

Dan

Jim,

One more question:  

1. Should one use a  constant input amplitude, close to the ~860mVpp, such that the Signal-to-Quantization noise is maximized on the ADC08D1520? 

Dan

Hi Dan

For the ADC08D1520, when the differential input signal is above positive full scale, the output will be all 1s with the OR (Out of Range) bit set. When the input signal is below negative full scale, the output will be all 0s with the OR bit set.

Best regards,

Jim B

Hi Dan

That is correct. The best Signal to Noise Ratio (SNR) performance will generally be achieved by keeping the input signal amplitude close to the maximum input full scale range.

Best regards,

Jim B