ADC12J4000 4GSPS

toshi-e2e

Other Parts Discussed in Thread: ADC12J4000, LMX2581, ADC12J4000EVM, TRF3765, LMK04828, LMK00301

Hi all,
My customer plans to use 8 units of ADC12J4000, and has some questions.

1. ADC12J4000EVM uses LMX2581 for ADC sampling clock and its sampling rate is upto 3.76GHz.
When ADC sampling clock is 4GHz, what device is recommended?
Also, is there the 4GSPS based reference circuit like ADC12J4000EVM?

2. When using 8 ADC's which are connected to one FPGA and all ADCs are synchronized,
are there any recommend clock ICs and the clock tree for this application?

I am happy to receive any advice on the design.

Regards,
Toshi

over 11 years ago

0 Jim Brinkhurst1 over 11 years ago

TI__Mastermind 44680 points

Hello

For item 1, we recommend using the TRF3765 as the clock source for 4 GSPS applications of the ADC12J4000. The latest reference circuit schematic is provided here:5756.Schematic Prints.PDF

I am working with a colleague on a recommendation for clocking a 10 ADC + 1 FPGA system. I hope to have that information in another day or two.

Regards,

Jim B

0 toshi-e2e over 11 years ago in reply to Jim Brinkhurst1

Genius 4830 points

Hello Jim-san,

Thanks for the latest reference circuit schematic.
I am looking forward to receiving a recommendation for clocking a 10 ADC + 1 FPGA.
I believe this is helpful for designing customer's application.

Best regards,
Toshi

0 toshi-e2e over 11 years ago in reply to toshi-e2e

Genius 4830 points

Hello Jim-san,

When can I get the clocking recommendation for 10 x ADC + one FPGA?

Thanks and regards,
Toshi

0 Jim Brinkhurst1 over 10 years ago in reply to toshi-e2e

TI__Mastermind 44680 points

Hi Toshi

Please see the proposed clocking scheme for 10 of the ADC12J4000 connected to 1 FPGA. If the customer can provide the intended operating mode and sample rate of the ADC12J4000 I will be able to provide more detail regarding the SYSREF frequency and reference clock rate for the TRF3765 and LMK04828 devices.

7343.Visio-10_ADC12J4000_4000MSPS_1FPGA_v2.pdf

Regards,

Jim B

0 toshi-e2e over 10 years ago in reply to Jim Brinkhurst1

Genius 4830 points

Hi Jim-san,

Thanks for the clock proposal.

These are customer's answers about your questions

1. Decimation setting is bypass ( no decimation).
2. Number of Lanes may be 8.
3. Sampling rate is 4 GSPS.

Regards,
Toshi

0 toshi-e2e over 10 years ago in reply to toshi-e2e

Genius 4830 points

Hi, Jim-san,

1. How do you determine the frequency of SYSREF and System Master Reference?

2. About SYSREF from LMK00301 to ADC, LMK00301 produces some delay. Is there no problem of timing
between ADC and FPGA?

3. When using two or more TRF3765, how do you synchronize output clock?
Whenever it switches on a power supply, it is anxious about timing, such as a rising edge of each output
waveform, becoming random.

Regards,

Toshi

0 Jim Brinkhurst1 over 10 years ago in reply to toshi-e2e

TI__Mastermind 44680 points

Hi Toshi

1. The SYSREF frequency (the master reference can have the same frequency) can be calculated from the sample rate operating mode and selected K (frames per multi-frame) settings. The spreadsheet attached here will help with those calculations.

5826.ADC12JXX00 SYSREF Dividers and Frequencies By Mode v2.xlsx

2. As long as the delay is relatively constant it will not cause issues with system synchronization. The plot below shows the propagation delay versus temperature for the LMK00301.

3. The TRF3765 output timing will be stable relative to the input reference clock provided the following settings are selected:

a) RDIV = 1 (The input reference clock must be used directly and not divided internally).

b) DIV1 is selected for the outputs. No divider used between the VCO selection MUX output and the RF output buffers.

c) Integer divide mode is used.

In these conditions the input reference clock and RF output will have a relatively constant phase alignment.

Best regards,

Jim B

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ADC12J4000 4GSPS