Hi,
We are using an ADS1294 in low power mode at 1k sampling rate with internal clock enabled.
The 1khz sampling clock is therefore derived from this internal clock. We've got good results overall, excepted that this sampling frequency from time to time, decreases by 6 to 9% on the five prototypes built so far.
The internal clock is the culprit. It slows down accordingly, as if it "locked" on a slower frequency (around 1,9Mhz instead of 2,053MHz when the oscillator works properly on all boards). This CLK signal is rather jittery with a quick frequency modulation of about 10kHz.
So the question is : is this oscillator built around a PLL or DPLL ? Is it very sensitive to noise ?
Thank you for your help.