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LM96551: Active Damper

Michael Query
Prodigy 20 points

The spec sheet for the LM96551 contains a block diagram (pg. 7) which shows an "Active Damper" block. The sheet also reads (pg. 7):

"When PIN and NIN are both LO, Vout is actively clamped to GNDHI at 0V. This clamping reduces harmonic
distortions compared to competing architectures that use bleeding resistors for implementing the return to zero of the output."

I need a bit more information about the "Active Damping" block. When considering the receive signal, will the V_out node be clamped to 0V when PIN and NIN are both LO? Or is "Active Damping" a set of FETs that will clamp the output to ±0.7V (or otherwise)?

Also is GNDHI the same as HVGND or AGND?

What more information can be disclosed about the "Active Damper"?

  • 0
    TI__Intellectual 1560 points

    Hi Michael,

    The active clamp will clamp the Vout to +/-0.7V. When there is a loading resistor at the output, Vout will then settle to 0V with a RC time constant. On fig 6 & 7 (page 9) of the datasheet, Rload is 100 Ohm & Cload is 330pF. 

    GNDHI is HVGND.

    Active clamp is similar to the output stage.

    Regards,

    Charles