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How to synchronize two ADS1675REF boards?

Gal Goldstein
Prodigy 20 points
Other Parts Discussed in Thread: ADCPRO, ADS1675

Hi

I have 2 boards of ADS1675REF.

I would like to operate them synchronously, so I need to put joint CLK and START.

1. Can I do that in the original FPGA code, and what are the setting command to do that?

2. Can I make one of the boards to be a slave of the other?

3. when doing so how do I read the data synchronously or how can I tell which sample is sync with the other ADC?

4. how can I read te sync data continiously for 5 minutes?

 

ThanKs

Gal

  • 0
    TI__Mastermind 23235 points

    Hi Gal and welcome to the TI E2E forums.

    As you may have noted, the datasheet has a section entitled Synchronizing Multiple ADS1675s, on page 25 that has a discussing of synchronize two devices and a block diagram of the connections.

    The schematic for the EVM is located on page 20 of the user guide, so you should be able to get to the correct signals to short together for testing.

    The EVM code is provided for evaluation purposes of a single device, so modifications to the hardware and software may be required to make this work.  We can provide the source code if you would like it for reference or a place to start, but we cannot support modifications/changes beyond the EVM application.

  • 0 in reply to Greg Hupp
    Prodigy 20 points

    Thanks

    I understand I have to do some HDL programing to make 2 boards working togeter.

    Gal

  • 0 in reply to Gal Goldstein
    Prodigy 50 points

    Hi!

    I am working with Gal, and when we started working we notice that the ISE ( the software that support programing the Xilink FPGA) can't synthesize the source code, because it missing a NGC file named "FIFO_GENERATOR_V2_3.ngc". also, the source code we found at the e2e forum is not organized - it contains a lot of unnecessary comments and it not clear enough for reverse engineering. it doesn't look like it is the final released version.

    Just like Gal mentioned above - the original source files are required for us because we want to make some changes in it before we download it to the FPGA, therefore we can't use the attached software ("ADCpro").

    1. i will be grateful if you can sent me all the source files required for this product (ADS1675 converter),which are in more clear and organized version.

    2. if you can't - just sent me the missing file (FIFO_GENERATOR_V2_3.ngc) please.

    3. we also need the XML file (the file that create the GUI in the ADCpro software, which can be loaded to the OpalKelly software named "FrontPanel" because we probably going to make some changes in it. also, this file will help us understand better and faster the original source files .

    thank,

    evyatar.

  • 0 in reply to evyatar dalkian
    TI__Mastermind 23235 points

    Hi Evyatar -

    Unfortunately, the files that are available is everything that we have.  The FIFO_GENERATOR file is from a ISE tool, so there is probably a newer version of it in the latest ISE/Xilinx toolset.

    The EVM software uses LabView, so there is no XML file for the FrontPanel tool.  We can provide the LabView source code if you would like, please let us know.  OpalKelly provides some example XML files that can be used to create your own FrontPanel; those can be obtained from OpalKelly download sight.  You will have to register with OpalKelly to get this software using the S/N of the OpalKelly board that came with the EVM.

  • 0 in reply to Greg Hupp
    Prodigy 50 points

    Hi
    the LabView source code will be helpful, and I will be glad to use it..
    thank you.

  • 0 in reply to evyatar dalkian
    TI__Mastermind 23235 points

    Hi Evyatar -

    You should receive an email to your profile email address.

    Please keep in mind the LV code does not work stand-alone as it is designed for the evaluation system only. You will need to modify the source to obtain this functionality.

  • 0 in reply to Greg Hupp
    Prodigy 80 points
    Hi Evyatar and Gal,

    I am currently having the same problems that you have mentioned above in this post. I am really interested in knowing if you managed to solve this problems and it would be really helpful if you could explain how you managed to do it.

    Thank you.

    Best regards,

    Albert Llimos