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DAC37J82 DAC Performance JESD Interface and PLL Settings

Michael Stibila
Prodigy 205 points

Other Parts Discussed in Thread: DAC37J82, TRF370417

I have a customer using the DAC37J82.    His proposed use case is described below.   He has a 240MHz low jitter clock that we can use for the DACCLKp,n ref input clock.  Please answer the questions below in RED.

                 Data rate:                            720 Msps

                Interpolation:                    2x

                DAC rate:                             1440 Msps

                Max bandwidth:               576 MHz

                DAC PLL:                              enabled

                DACCLKp,n input:            240 MHz, with jitter 100fs-rms

                LMF:                                      421   (using 4 SerDes lanes)

                SerDes line rate:               7.2 Gbps

 

                Sinx/x correction:            enabled

                Quadrature modulator correction:           enabled

                DC offset correction:      enabled

                Group delay correction:  enabled

               NCO, mixer:                       TBD

                 DAC PLL settings:             ref = 240MHz, N = 1, Prescaler = 3, M = 6, VCO = 4320MHz

                SerDes PLL settings:       

Option a)    refclk source: DACCLKp,n input (240MHz), REFCLK_DIV = 2, MPY = 15, ‘Full Rate’, VCO = 1800MHz

Option b)    refclk source: internal DAC PLL output (1440MHz), REFCLK_DIV = 4, MPY = 5, ‘Full Rate’, VCO = 1800MHz

 Questions:

- Which of the above ‘SerDes PLL settings’ options is recommended for best performance?

- What performance can we expect using the DAC PLL with low jitter ref clock input?   Note: the datasheet’s performance plots are for DAC PLL bypassed.

- what is allowable range of the SERDES PLL refclk divider?   It’s not mentioned in the datasheet.

- what is the recommended BWSCALE setting for our application?

- do you recommend that we use internal or external DAC PLL loop filter for our application?

- can the VDDAPLL18, VDDAREF18, VDDIO18, VDDR18, VDDS18, VQPS18 come from the same +1.8V power supply?

- can the VDDDAC09, VDDCLK09, VDDDIG09, VDDT09 come from the same +0.9V power supply?

- can you provide instructions for interfacing the DAC37J82 outputs with analog reconstruction filters and the TI TRF370417 IQ modulator?

  • 0
    TI__Genius 17480 points

    Hi Michael,

    - Which of the above ‘SerDes PLL settings’ options is recommended for best performance?

    [Matt] Generally whichever gives the highest reference frequency, so option B. There are a lot of question marks here though, so it would be best to simply test the serdes BER using PRBS testing for each case. This only requires a register change, so no hardware changes would be needed to switch between the two options.

    - What performance can we expect using the DAC PLL with low jitter ref clock input?   Note: the datasheet’s performance plots are for DAC PLL bypassed.

    [Matt] There are plots intermixed showing performance (SFDR, IMD3, NSD, etc) with PLL on. See figure 9, 17, 25. Phase noise will likely be worse than if a very high quality external clock were used.

    - what is allowable range of the SERDES PLL refclk divider?   It’s not mentioned in the datasheet.

    [Matt] Range is divide by 1 to divide by 16.

    - what is the recommended BWSCALE setting for our application?

    [Matt] The loop bandwidth (LB in config60) parameter should be set to 00. The only reason to touch this parameter is if your measured BER does not meet your system requirements.

    - do you recommend that we use internal or external DAC PLL loop filter for our application?

    [Matt] Internal, but it wouldn't hurt to have placeholders for external loop filter. If placeholders are used, I would suggest placing a 0ohm series resistor in the path to disconnect it from the chip if not used.

    - can the VDDAPLL18, VDDAREF18, VDDIO18, VDDR18, VDDS18, VQPS18 come from the same +1.8V power supply?

    [Matt] Yes, but we suggest keeping them separated by ferrite beads. See EVM schematic. VDDAPLL is the biggest concern if using the DAC PLL.

    - can the VDDDAC09, VDDCLK09, VDDDIG09, VDDT09 come from the same +0.9V power supply?

    [Matt] VDDDIG should be kept separate since this will have lots of digital switching noise. The others can be shared but should be isolated. VDDCLK is the biggest concern.

    - can you provide instructions for interfacing the DAC37J82 outputs with analog reconstruction filters and the TI TRF370417 IQ modulator?

    [Matt] Yes, I will follow up.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Intellectual 585 points

    Hi Matt,

    I'm working with Mike Stibila on this project.     Can you provide an app note or schematic for interfacing the DAC37J82 outputs to the TI TRF370417 IQ modulator?    With reconstruction filters in between.  

    In the past, we've AC coupled between the another (competitors) DAC and the TRF370417, but we also had auxiliary DACs that could be used for DC offset correction (LO bleedthru).   We don't have that capability with the DAC37J82, so I think we must be DC coupled.


    thanks,  Scott

  • 0 in reply to Scott Greeley1
    TI__Genius 17480 points

    Hi Scott,

    Please send me your e-mail and I'll send you a preliminary report. I'll add you as a friend on E2E so you can send it privately. The report will be posted to ti.com soon.

    Regards,
    Matt Guibord