AFE5805 noise

Danilo,

We have received your post and should have a response back to you soon.

Hello, Thanks for contacting TI.  Sorry to hear you are having problems getting your system up and running. Looking at your matlab rendering the problem looks digital in nature.  Have you tested the digital back end to confirm data capture and transfer up the PC is correct?  If you haven’t, I suggest programming the AFE5805 to output RAMP LVDS test pattern (see page 31 of the datasheet for more information).  In this mode you know exactly what you should receive from the AFE5805 and can focus on FPGA and PC side code for potential problems.

I am confident you'll find the solution.  Post back if you need any help or have resolved the problem.

Thanks Lijoy,

I tried it that you told me and the data still came with noise. Analyzing these binary data I realized that generally is one bit wrong. I entered with an external clock and for slower clock frequencies data come perfect. So I think I'm having problems with Timing on my FPGA (Stratix IV).

I tried to solve it using "optimization timing" and writing an sdc file, informing false paths and clock frequencies, but again without success. 

I know that if a change the internal clock for 30MHz crystal I will solve this problem, but I would prefer to look for a different solution 

Do you have any tips to me? 

Thank you 

Danilo Camara

Hi Danilo,

I'm happy to hear you found the problem and to a large extend also understand it.  Have you used the Xilinx delay line elements?  I'm not an expert on FPGAs, but I believe those delay line elements give quite a bit of flexibility. 

Have you looked at the LVDS signals on o'scope to see the timing margins?  Is it within specifications?  The root cause of your problem is very likely in your layout, maybe signal lines are not length and/or impedance matched, as well as they need to me. Do you have the ability to change the termination resistors on the signal lines?  If so, try to tune your termination resistors to increase signal integrity enough to remove that error bit.  I would start by looking at the signals on o'scope first and change one thing at a time and see it's effect.

Good luck. 

Best Regards,

Lijoy

Have you looked at the LVDS signals on o'scope to see the timing margins? 

Unfortunately I can't do that because I don't have sample frequency enough  to see 240MHz.

I tried to use the texas firmware to AFE (afe5808_12b) and the data come perfect there, so I think that this is not a impedance matching problem. I developed a 8ch emission code with beamforming, pulse coding, frequency and PRF control, and I would like to integrate it with acquisition code. Could you provide me this project, not just the rbf file?  

* some time ago TI send me a project but it is for ADS62P49, but this board have 2ch and send parallel data to FPGA. 

Thank you

Danilo

Hi Danilo,

We aren't experts in FPGA design, but I might be able to help get started.  Let's take the conversation offline.

Regards,

Lijoy